>>> On 16.04.18 at 12:56, <andrew.coop...@citrix.com> wrote:
> The behaviour of reserved bits in MSR_PRED_CMD changed between beta and
> production microcode, and now raises a #GP fault for set reserved bits.

Interesting - quite unfortunate a change. Plus - I can't find where this is 
being
said.

> The AMD spec for future hardware also specifies this behaviour.

I can find this one (albeit not in the PRM).

> Signed-off-by: Andrew Cooper <andrew.coop...@citrix.com>

With some clarification on the origin of the Intel related information
Reviewed-by: Jan Beulich <jbeul...@suse.com>

Jan



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