On 16/04/18 12:12, Jan Beulich wrote:
>>>> On 16.04.18 at 12:56, <andrew.coop...@citrix.com> wrote:
>> The behaviour of reserved bits in MSR_PRED_CMD changed between beta and
>> production microcode, and now raises a #GP fault for set reserved bits.
> Interesting - quite unfortunate a change. Plus - I can't find where this is 
> being
> said.

Its not, but the new behaviour can be demonstrated easily.  Those with
the beta microcode can confirm that the old behaviour was to ignore.

FWIW, ignoring reserved bits was always dubious, and I only implemented
it like that to match how hardware behaved.  This new behaviour is far
more sane.

>
>> The AMD spec for future hardware also specifies this behaviour.
> I can find this one (albeit not in the PRM).

Its still in whitepaper form. 

https://developer.amd.com/wp-content/resources/Architecture_Guidelines_Update_Indirect_Branch_Control.pdf

"Indirect branch prediction barrier (IBPB) exists at MSR 0x49 (PRED_CMD)
bit 0. This is a write only MSR that both GP faults when software reads
it or if software tries to write any of the bits in 63:1"

~Andrew

>
>> Signed-off-by: Andrew Cooper <andrew.coop...@citrix.com>
> With some clarification on the origin of the Intel related information
> Reviewed-by: Jan Beulich <jbeul...@suse.com>
>
> Jan
>
>


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