Hi Julien, > -----Original Message----- > Subject: [PATCH v4 08/14] xen/arm32: head: Introduce an helper to flush the > TLBs > > From: Julien Grall <jgr...@amazon.com> > > The sequence for flushing the TLBs is 4 instruction long and often > requires an explanation how it works. > > So create a helper and use it in the boot code (switch_ttbr() is left > alone until we decide the semantic of the call). > > Note that in secondary_switched, we were also flushing the instruction > cache and branch predictor. Neither of them was necessary because: > * We are only supporting IVIPT cache on arm32, so the instruction > cache flush is only necessary when executable code is modified. > None of the boot code is doing that. > * The instruction cache is not invalidated and misprediction is not > a problem at boot. > > Signed-off-by: Julien Grall <jgr...@amazon.com>
Reviewed-by: Henry Wang <henry.w...@arm.com> I've also tested this patch on FVP in arm32 execution mode, and this patch is good, so: Tested-by: Henry Wang <henry.w...@arm.com> Kind regards, Henry
