Nowadays AMD supports trapping the CPUID instruction from ring3 to ring0, (CpuidUserDis) akin to Intel's "CPUID faulting". There is a difference in that the toggle bit is in a different MSR and the support bit is in CPUID itself rather than yet another MSR. This patch enables AMD hosts to use it when supported in order to provide correct CPUID contents to PV guests. Also allows HVM guests to use CpuidUserDis via emulated "CPUID faulting".
Patch 1 merely adds definitions to various places in CPUID and MSR Patch 2 adds support for CpuidUserDis, hooking it in the probing path and the context switching path. Patch 3 enables HVM guests to use CpuidUserDis as if it was CPUID faulting, saving an avoidable roundtrip through the hypervisor at fault handling. Alejandro Vallejo (3): x86: Add AMD's CpuidUserDis bit definitions x86: Add support for CpuidUserDis x86: Use CpuidUserDis if an AMD HVM guest toggles CPUID faulting tools/libs/light/libxl_cpuid.c | 1 + tools/misc/xen-cpuid.c | 2 + xen/arch/x86/cpu/amd.c | 29 +++++++++++- xen/arch/x86/cpu/common.c | 51 +++++++++++---------- xen/arch/x86/cpu/intel.c | 11 ++++- xen/arch/x86/include/asm/amd.h | 1 + xen/arch/x86/include/asm/msr-index.h | 1 + xen/arch/x86/msr.c | 9 +++- xen/include/public/arch-x86/cpufeatureset.h | 1 + 9 files changed, 79 insertions(+), 27 deletions(-) -- 2.34.1
