Hi Michal,
> -----Original Message-----
> Subject: [PATCH 3/4] xen/arm: pl011: Use correct accessors
>
> At the moment, we use 32-bit only accessors (i.e. readl/writel) to match
> the SBSA v2.x requirement. This should not be the default case for normal
> PL011 where accesses shall be 8/16-bit (max register size is 16-bit).
> There are however implementations of this UART that can only handle 32-bit
> MMIO. This is advertised by dt property "reg-io-width" set to 4.
>
> Introduce new struct pl011 member mmio32 and replace pl011_{read/write}
> macros with static inline helpers that use 32-bit or 16-bit accessors
> (largest-common not to end up using different ones depending on the actual
> register size) according to mmio32 value. By default this property is set
> to false, unless:
> - reg-io-width is specified with value 4,
> - SBSA UART is in use.
>
> For now, no changes done for ACPI due to lack of testing possibilities
> (i.e. current behavior maintained resulting in 32-bit accesses).
>
> Signed-off-by: Michal Orzel <michal.or...@amd.com>
I've tested this patch on top of today's staging on FVP arm32 and arm64 and
confirm this patch will not break existing functionality. So:
Tested-by: Henry Wang <henry.w...@arm.com>
Kind regards,
Henry
