Hello, Following series attempts to solve the issue with IO-APIC edge triggered interrupts seeing an inconsistent IRTE when injected while being migrated.
It's been simplified a bit from the original RFC, and does make the logic in the IOMMU RTE update handlers cleaner, as those get passed the full RTE. When not using interrupt remapping the logic is left as-is. One further change would be to mask edge triggered interrupts, as destination and vector cannot be changed atomically when dealing with plain IO-APIC RTEs. Last patch has also been adjusted in order to always to atomic IRTE updates on AMD. Thanks, Roger. Roger Pau Monne (5): x86/ioapic: add a raw field to RTE struct x86/ioapic: RTE modifications must use ioapic_write_entry iommu/vtd: rename io_apic_read_remap_rte() local variable x86/iommu: pass full IO-APIC RTE for remapping table update amd/iommu: force atomic updates of remapping entries xen/arch/x86/include/asm/io_apic.h | 65 +++++----- xen/arch/x86/include/asm/iommu.h | 3 +- xen/arch/x86/io_apic.c | 40 +++--- xen/drivers/passthrough/amd/iommu.h | 2 +- xen/drivers/passthrough/amd/iommu_init.c | 10 ++ xen/drivers/passthrough/amd/iommu_intr.c | 155 +++-------------------- xen/drivers/passthrough/vtd/extern.h | 2 +- xen/drivers/passthrough/vtd/intremap.c | 131 ++++++++++--------- xen/drivers/passthrough/x86/iommu.c | 4 +- xen/include/xen/iommu.h | 3 +- 10 files changed, 156 insertions(+), 259 deletions(-) -- 2.41.0
