Introduce a handler for the PCI status register, with ability to mask the
capabilities bit. The status register contains reserved bits, read-only bits,
and write-1-to-clear bits, so introduce bitmasks to handle these in vPCI. If a
bit in the bitmask is set, then the special meaning applies:
res_mask: read as zero, write ignore
ro_mask: read normal, write ignore
rw1c_mask: read normal, write 1 to clear
The mask_cap_list flag will be set in a follow-on patch.
Signed-off-by: Stewart Hildebrand <stewart.hildebr...@amd.com>
---
v4->v5:
* add support for res_mask
* add support for ro_mask (squash ro_mask patch)
* add constants for reserved, read-only, and rw1c masks
v3->v4:
* move mask_cap_list setting to the capabilities patch
* single pci_conf_read16 in status_read
* align mask_cap_list bitfield in struct vpci_header
* change to rw1c bit mask instead of treating whole register as rw1c
* drop subsystem prefix on renamed add_register function
v2->v3:
* new patch
---
xen/drivers/vpci/header.c | 18 +++++++++++++++
xen/drivers/vpci/vpci.c | 46 +++++++++++++++++++++++++++++++-------
xen/include/xen/pci_regs.h | 8 +++++++
xen/include/xen/vpci.h | 10 +++++++++
4 files changed, 74 insertions(+), 8 deletions(-)
diff --git a/xen/drivers/vpci/header.c b/xen/drivers/vpci/header.c
index 767c1ba718d7..791791e6c9b6 100644
--- a/xen/drivers/vpci/header.c
+++ b/xen/drivers/vpci/header.c
@@ -413,6 +413,18 @@ static void cf_check cmd_write(
pci_conf_write16(pdev->sbdf, reg, cmd);
}
+static uint32_t cf_check status_read(const struct pci_dev *pdev,
+ unsigned int reg, void *data)
+{
+ struct vpci_header *header = data;
+ uint32_t status = pci_conf_read16(pdev->sbdf, reg);
+
+ if ( header->mask_cap_list )
+ status &= ~PCI_STATUS_CAP_LIST;
+
+ return status;
+}
+
static void cf_check bar_write(
const struct pci_dev *pdev, unsigned int reg, uint32_t val, void *data)
{
@@ -544,6 +556,12 @@ static int cf_check init_bars(struct pci_dev *pdev)
if ( rc )
return rc;
+ rc = vpci_add_register_mask(pdev->vpci, status_read, vpci_hw_write16,
+ PCI_STATUS, 2, header,
PCI_STATUS_RESERVED_MASK,
+ PCI_STATUS_RO_MASK, PCI_STATUS_RW1C_MASK);
+ if ( rc )
+ return rc;
+
if ( pdev->ignore_bars )
return 0;
diff --git a/xen/drivers/vpci/vpci.c b/xen/drivers/vpci/vpci.c
index 3bec9a4153da..6e6ad4b80a0d 100644
--- a/xen/drivers/vpci/vpci.c
+++ b/xen/drivers/vpci/vpci.c
@@ -29,6 +29,9 @@ struct vpci_register {
unsigned int offset;
void *private;
struct list_head node;
+ uint32_t res_mask;
+ uint32_t ro_mask;
+ uint32_t rw1c_mask;
};
#ifdef __XEN__
@@ -145,9 +148,16 @@ uint32_t cf_check vpci_hw_read32(
return pci_conf_read32(pdev->sbdf, reg);
}
-int vpci_add_register(struct vpci *vpci, vpci_read_t *read_handler,
- vpci_write_t *write_handler, unsigned int offset,
- unsigned int size, void *data)
+void cf_check vpci_hw_write16(
+ const struct pci_dev *pdev, unsigned int reg, uint32_t val, void *data)
+{
+ pci_conf_write16(pdev->sbdf, reg, val);
+}
+
+static int add_register(struct vpci *vpci, vpci_read_t *read_handler,
+ vpci_write_t *write_handler, unsigned int offset,
+ unsigned int size, void *data, uint32_t res_mask,
+ uint32_t ro_mask, uint32_t rw1c_mask)
{
struct list_head *prev;
struct vpci_register *r;
@@ -167,6 +177,9 @@ int vpci_add_register(struct vpci *vpci, vpci_read_t
*read_handler,
r->size = size;
r->offset = offset;
r->private = data;
+ r->res_mask = res_mask & (0xffffffffU >> (32 - 8 * size));
+ r->ro_mask = ro_mask & (0xffffffffU >> (32 - 8 * size));
+ r->rw1c_mask = rw1c_mask & (0xffffffffU >> (32 - 8 * size));
spin_lock(&vpci->lock);
@@ -193,6 +206,23 @@ int vpci_add_register(struct vpci *vpci, vpci_read_t
*read_handler,
return 0;
}
+int vpci_add_register(struct vpci *vpci, vpci_read_t *read_handler,
+ vpci_write_t *write_handler, unsigned int offset,
+ unsigned int size, void *data)
+{
+ return add_register(vpci, read_handler, write_handler, offset, size, data,
+ 0, 0, 0);
+}
+
+int vpci_add_register_mask(struct vpci *vpci, vpci_read_t *read_handler,
+ vpci_write_t *write_handler, unsigned int offset,
+ unsigned int size, void *data, uint32_t res_mask,
+ uint32_t ro_mask, uint32_t rw1c_mask)
+{
+ return add_register(vpci, read_handler, write_handler, offset, size, data,
+ res_mask, ro_mask, rw1c_mask);
+}
+
int vpci_remove_register(struct vpci *vpci, unsigned int offset,
unsigned int size)
{
@@ -376,6 +406,7 @@ uint32_t vpci_read(pci_sbdf_t sbdf, unsigned int reg,
unsigned int size)
}
val = r->read(pdev, r->offset, r->private);
+ val &= ~r->res_mask;
/* Check if the read is in the middle of a register. */
if ( r->offset < emu.offset )
@@ -407,11 +438,6 @@ uint32_t vpci_read(pci_sbdf_t sbdf, unsigned int reg,
unsigned int size)
/*
* Perform a maybe partial write to a register.
- *
- * Note that this will only work for simple registers, if Xen needs to
- * trap accesses to rw1c registers (like the status PCI header register)
- * the logic in vpci_write will have to be expanded in order to correctly
- * deal with them.
*/
static void vpci_write_helper(const struct pci_dev *pdev,
const struct vpci_register *r, unsigned int size,
@@ -424,9 +450,13 @@ static void vpci_write_helper(const struct pci_dev *pdev,
uint32_t val;
val = r->read(pdev, r->offset, r->private);
+ val &= ~r->res_mask;
+ val &= ~r->rw1c_mask;
data = merge_result(val, data, size, offset);
}
+ data &= ~r->res_mask;
+ data &= ~r->ro_mask;
r->write(pdev, r->offset, data & (0xffffffffU >> (32 - 8 * r->size)),
r->private);
}
diff --git a/xen/include/xen/pci_regs.h b/xen/include/xen/pci_regs.h
index 84b18736a85d..b7cb200969c6 100644
--- a/xen/include/xen/pci_regs.h
+++ b/xen/include/xen/pci_regs.h
@@ -66,6 +66,14 @@
#define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
#define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
+#define PCI_STATUS_RESERVED_MASK 0x06
+#define PCI_STATUS_RO_MASK (PCI_STATUS_IMM_READY | PCI_STATUS_INTERRUPT | \
+ PCI_STATUS_CAP_LIST | PCI_STATUS_CAP_LIST | PCI_STATUS_66MHZ | \
+ PCI_STATUS_UDF | PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MASK)
+#define PCI_STATUS_RW1C_MASK (PCI_STATUS_PARITY | \
+ PCI_STATUS_SIG_TARGET_ABORT | PCI_STATUS_REC_TARGET_ABORT | \
+ PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_SIG_SYSTEM_ERROR | \
+ PCI_STATUS_DETECTED_PARITY)
#define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8
revision */
#define PCI_REVISION_ID 0x08 /* Revision ID */
diff --git a/xen/include/xen/vpci.h b/xen/include/xen/vpci.h
index 0b8a2a3c745b..0a6c9e19b399 100644
--- a/xen/include/xen/vpci.h
+++ b/xen/include/xen/vpci.h
@@ -37,6 +37,12 @@ int __must_check vpci_add_register(struct vpci *vpci,
vpci_write_t *write_handler,
unsigned int offset, unsigned int size,
void *data);
+int __must_check vpci_add_register_mask(struct vpci *vpci,
+ vpci_read_t *read_handler,
+ vpci_write_t *write_handler,
+ unsigned int offset, unsigned int size,
+ void *data, uint32_t res_mask,
+ uint32_t ro_mask, uint32_t rw1c_mask);
int __must_check vpci_remove_register(struct vpci *vpci, unsigned int offset,
unsigned int size);
@@ -50,6 +56,8 @@ uint32_t cf_check vpci_hw_read16(
const struct pci_dev *pdev, unsigned int reg, void *data);
uint32_t cf_check vpci_hw_read32(
const struct pci_dev *pdev, unsigned int reg, void *data);
+void cf_check vpci_hw_write16(
+ const struct pci_dev *pdev, unsigned int reg, uint32_t val, void *data);
/*
* Check for pending vPCI operations on this vcpu. Returns true if the vcpu
@@ -94,6 +102,8 @@ struct vpci {
* upon to know whether BARs are mapped into the guest p2m.
*/
bool bars_mapped : 1;
+ /* Store whether to hide all capabilities from the guest. */
+ bool mask_cap_list : 1;
/* FIXME: currently there's no support for SR-IOV. */
} header;
--
2.42.0
