On 13/10/2023 10:33 pm, Alejandro Vallejo wrote: > On Fri, Oct 13, 2023 at 09:40:52PM +0800, Andrew Cooper wrote: >> On 13/10/2023 9:18 pm, Alejandro Vallejo wrote: >> This will surely be a core scope MSR rather than thread scope, > It is, though I doubt it matters a whole lot. The writes are consistent > anyway.
This happens to be true because you introduced the first use of the MSR. It ceases to be true for the next chickenbit in this MSR, which is why ... >> at which >> point the write ought to be conditional on seeing the chickenbit >> clear (hence needing to refer to the value at least twice, so use a >> local variable). > I have serious doubts such a conditional would do much for boot times, but > sure. ... this is not about boot time. It's about avoiding an unnecessary non-atomic action. (TBH, when the second chickenbit comes, it's all suspect anyway and probably needs to end up like the pre-SSBD handling, which has horrifying complexity.) ~Andrew
