GICD_CTL_ENABLE is a GICv2 bit. Remove it. The definitions of
GICD_CTL_ENABLE and GICD_CTLR_ENABLE_G1 are identical, so the value
written is unchanged.
Signed-off-by: Stewart Hildebrand <stewart.hildebr...@amd.com>
---
xen/arch/arm/gic-v3.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c
index 172ff8c005ff..9b35a8c8a735 100644
--- a/xen/arch/arm/gic-v3.c
+++ b/xen/arch/arm/gic-v3.c
@@ -633,8 +633,8 @@ static void __init gicv3_dist_init(void)
gicv3_dist_wait_for_rwp();
/* Turn on the distributor */
- writel_relaxed(GICD_CTL_ENABLE | GICD_CTLR_ARE_NS |
- GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1, GICD + GICD_CTLR);
+ writel_relaxed(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A |
+ GICD_CTLR_ENABLE_G1, GICD + GICD_CTLR);
/* Route all global IRQs to this CPU */
affinity = gicv3_mpidr_to_affinity(smp_processor_id());
base-commit: c22fe7213c9b1f99cbc64c33e391afa223f9cd08
--
2.43.0
