On 28/08/2024 7:08 pm, Andrew Cooper wrote:
> On 28/08/2024 10:19 am, Jan Beulich wrote:
>> On 27.08.2024 15:57, Andrew Cooper wrote:
>>> + * get it back again.
>>> + */
>>> + for ( unsigned int i = 0; i < ARRAY_SIZE(vec._64); ++i )
>>> + vec._64[i] = xchg(&desc->pir[i], 0);
>>> +
>>> + /*
>>> + * Finally, merge the pending vectors into IRR. The IRR register is
>>> + * scattered in memory, so we have to do this 32 bits at a time.
>>> + */
>>> + irr = (uint32_t *)&vcpu_vlapic(v)->regs->data[APIC_IRR];
>>> + for ( unsigned int i = 0; i < ARRAY_SIZE(vec._32); ++i )
>>> + {
>>> + if ( !vec._32[i] )
>>> + continue;
>>>
>>> - bitmap_for_each ( i, pending_intr, X86_NR_VECTORS )
>>> - vlapic_set_vector(i, &vlapic->regs->data[APIC_IRR]);
>>> + asm ( "lock or %[val], %[irr]"
>>> + : [irr] "+m" (irr[i * 0x10])
>> This wants to be irr * 4 only, to account for sizeof(*irr) == 4.
> Ah, that will be where the AlderLake interrupts are disappearing to.
Indeed. It's much happier now.
https://gitlab.com/xen-project/people/andyhhp/xen/-/pipelines/1431047447
~Andrew
