On 08/09/2024 22:13, Julien Grall wrote:
Hi,
Hi Julien,
On 02/09/2024 15:48, Ayan Kumar Halder wrote:
I will rephrase this as ...
"Used to set customized address at which which Xen will be linked
on MPU systems. This address must be aligned to a page size.
0xFFFFFFFF is used as the default value to indicate that user hasn't
customized this address."
Reading this comment, I would like to ask some clarification. In the
context of the MPU how do you define a page size? The definition is
pretty clear when using the MMU because the granularity if defined by
the HW. But for the MPU, it is a bit blur. Is it still 4KB? If so, is
it actually realistic (we don't have that many MPU regions)?
From ARM DDI 0600A.d ID120821, C1.1.1 Protection regions
"Protection regions have a minimum size of 64 bytes."
Thus, I would infer that the minimum page size (in context of MPU) is 64
bytes.
Also, if you see the register fields of PRBAR and PRLAR, the lower 6
bits are 0 extended to provide the address.
So, may be I should say
".... address must be aligned to the minimum region size (ie 64 bytes).
0xFFFFFFFF is used ...."
Let me know if this sounds ok.
- Ayan
