Hi Michal,
> On 3 Sep 2024, at 14:21, Michal Orzel <michal.or...@amd.com> wrote:
>
> According to GIC spec IHI 0069H.b (12.4.9), the ListRegs field of
> ICH_VTR_EL2 can have value between 0b00000..0b01111, as there can
> be maximum 16 LRs (field value + 1). Fix the mask used to extract this
> value which wrongly assumes there can be 64 (case for GICv2).
>
> Fixes: bc183a0235e0 ("xen/arm: Add support for GIC v3")
> Signed-off-by: Michal Orzel <michal.or...@amd.com>
Nice finding.
Reviewed-by: Bertrand Marquis <bertrand.marq...@arm.com>
Cheers
Bertrand
> ---
> xen/arch/arm/include/asm/gic_v3_defs.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/xen/arch/arm/include/asm/gic_v3_defs.h
> b/xen/arch/arm/include/asm/gic_v3_defs.h
> index 227533868f8d..2af093e774e5 100644
> --- a/xen/arch/arm/include/asm/gic_v3_defs.h
> +++ b/xen/arch/arm/include/asm/gic_v3_defs.h
> @@ -189,7 +189,7 @@
> #define ICH_LR_GRP1 (1ULL << 60)
> #define ICH_LR_HW (1ULL << 61)
>
> -#define ICH_VTR_NRLRGS 0x3f
> +#define ICH_VTR_NRLRGS 0xf
> #define ICH_VTR_PRIBITS_MASK 0x7
> #define ICH_VTR_PRIBITS_SHIFT 29
>
> --
> 2.25.1
>
