On 15.08.2025 22:41, Andrew Cooper wrote:
> The TSC functionality is only related to MSRs by write_tsc(), and this really
> does not want to be available as widely as is currently is.
>
> asm/time.h shouldn't be including asm/msr.h, but this turns out to be
> sufficiently tangled that I've chosen to break it out into it's own patch.
>
> No functional change.
>
> Signed-off-by: Andrew Cooper <andrew.coop...@citrix.com>
Acked-by: Jan Beulich <jbeul...@suse.com>
with one nit:
> --- /dev/null
> +++ b/xen/arch/x86/include/asm/tsc.h
> @@ -0,0 +1,46 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +#ifndef X86_TSC_H
> +#define X86_TSC_H
> +
> +#include <asm/alternative.h>
> +
> +static inline uint64_t rdtsc(void)
> +{
> + uint64_t low, high;
> +
> + asm volatile ( "rdtsc" : "=a" (low), "=d" (high) );
> +
> + return (high << 32) | low;
> +}
> +
> +static inline uint64_t rdtsc_ordered(void)
> +{
> + uint64_t low, high, aux;
> +
> + /*
> + * The RDTSC instruction is not serializing. Make it dispatch
> serializing
> + * for the purposes here by issuing LFENCE (or MFENCE if necessary) ahead
> + * of it.
> + *
> + * RDTSCP, otoh, "does wait until all previous instructions have executed
> + * and all previous loads are globally visible" (SDM) / "forces all older
> + * instructions to retire before reading the timestamp counter" (APM).
> + */
> + alternative_io_2("lfence; rdtsc",
> + "mfence; rdtsc", X86_FEATURE_MFENCE_RDTSC,
> + "rdtscp", X86_FEATURE_RDTSCP,
> + ASM_OUTPUT2("=a" (low), "=d" (high), "=c" (aux)),
> + /* no inputs */);
> +
> + return (high << 32) | low;
> +}
> +
> +#define __write_tsc(val) wrmsrl(MSR_IA32_TSC, val)
> +#define write_tsc(val) ({ \
> + /* Reliable TSCs are in lockstep across all CPUs. We should \
> + * never write to them. */ \
This comment may want to become a proper Xen-style one while being moved.
Jan
