[PATCH 2/2] x86/mce: Adjustments to intel_init_ppin()

[Andrew Cooper]

There's no family check gating intel_init_ppin(), making it incorrect to use
on non Fam6 CPUs.  Switch to using VFM.

Emerald Rapids is the final CPU to have PPIN but lack the the architectural
enumeration, so include it too.

Signed-off-by: Andrew Cooper <andrew.coop...@citrix.com>
---
CC: Jan Beulich <jbeul...@suse.com>
CC: Roger Pau Monné <roger....@citrix.com>
---
 xen/arch/x86/cpu/mcheck/mce_intel.c | 20 +++++++++++---------
 1 file changed, 11 insertions(+), 9 deletions(-)

diff --git a/xen/arch/x86/cpu/mcheck/mce_intel.c 
b/xen/arch/x86/cpu/mcheck/mce_intel.c
index d1d61bc95069..16f286566ce7 100644
--- a/xen/arch/x86/cpu/mcheck/mce_intel.c
+++ b/xen/arch/x86/cpu/mcheck/mce_intel.c
@@ -9,6 +9,7 @@
 #include <xen/smp.h>
 
 #include <asm/apic.h>
+#include <asm/intel-family.h>
 #include <asm/mce.h>
 #include <asm/msr.h>
 #include <asm/p2m.h>
@@ -859,7 +860,7 @@ static void intel_init_ppin(const struct cpuinfo_x86 *c)
      * other purposes.  Despite the late addition of a CPUID bit (rendering
      * the MSR architectural), keep using the same detection logic there.
      */
-    switch ( c->x86_model )
+    switch ( c->vfm )
     {
         uint64_t val;
 
@@ -870,14 +871,15 @@ static void intel_init_ppin(const struct cpuinfo_x86 *c)
             return;
         }
         fallthrough;
-    case 0x3e: /* IvyBridge X */
-    case 0x3f: /* Haswell X */
-    case 0x4f: /* Broadwell X */
-    case 0x55: /* Skylake X */
-    case 0x56: /* Broadwell Xeon D */
-    case 0x6a: /* Icelake X */
-    case 0x6c: /* Icelake D */
-    case 0x8f: /* Sapphire Rapids X */
+    case INTEL_IVYBRIDGE_X:
+    case INTEL_HASWELL_X:
+    case INTEL_BROADWELL_X:
+    case INTEL_BROADWELL_D:
+    case INTEL_SKYLAKE_X:
+    case INTEL_ICELAKE_X:
+    case INTEL_ICELAKE_D:
+    case INTEL_SAPPHIRERAPIDS_X:
+    case INTEL_EMERALDRAPIDS_X:
 
         if ( (c != &boot_cpu_data && !ppin_msr) ||
              rdmsr_safe(MSR_PPIN_CTL, val) )
-- 
2.39.5