To properly deactivate physical eSPI routed to a domain and allow them to be retriggered after the initial trigger, the LR needs to be updated. The current implementation ignores interrupts outside the range specified by the mask 0x3FF, which only covers IRQ numbers up to 1023. To enable processing of eSPI interrupts, this patch updates the mask to 0x1FFF.
Signed-off-by: Leonid Komarianskyi <leonid_komarians...@epam.com> --- Changes in V6: - updated mask to 0x1fff to avoid confusion - updated commit message - removed reviewed-by as new changes requires additional confirmation from reviewers Changes in V5: - no changes Changes in V4: - added reviewed-by from Volodymyr Babchuk Changes in V3: - no changes Changes in V2: - remove unnecessary CONFIG_GICV3_ESPI ifdef guard --- xen/arch/arm/include/asm/gic_v3_defs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/arch/arm/include/asm/gic_v3_defs.h b/xen/arch/arm/include/asm/gic_v3_defs.h index 3370b4cd52..c373b94d19 100644 --- a/xen/arch/arm/include/asm/gic_v3_defs.h +++ b/xen/arch/arm/include/asm/gic_v3_defs.h @@ -211,7 +211,7 @@ #define ICH_LR_VIRTUAL_SHIFT 0 #define ICH_LR_CPUID_MASK 0x7 #define ICH_LR_CPUID_SHIFT 10 -#define ICH_LR_PHYSICAL_MASK 0x3ff +#define ICH_LR_PHYSICAL_MASK 0x1fff #define ICH_LR_PHYSICAL_SHIFT 32 #define ICH_LR_STATE_MASK 0x3 #define ICH_LR_STATE_SHIFT 62 -- 2.34.1
