[PATCH 1/3] x86/amd: Fold another DE_CFG edit into amd_init_de_cfg()

[Andrew Cooper]

Fam12h processors aren't SMT-capable so there are no race condition worries
with this path.  Nevertheless, group it together with the other DE_CFG
modifications.

Fixes: d0c75dc4c028 ("x86/amd: Fix race editing DE_CFG")
Signed-off-by: Andrew Cooper <andrew.coop...@citrix.com>
---
CC: Jan Beulich <jbeul...@suse.com>
CC: Roger Pau Monné <roger....@citrix.com>

I apparently couldn't count how many examples we had editing DE_CFG...
---
 xen/arch/x86/cpu/amd.c | 16 +++++++---------
 1 file changed, 7 insertions(+), 9 deletions(-)

diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c
index 47c109f89804..4dc9157836ad 100644
--- a/xen/arch/x86/cpu/amd.c
+++ b/xen/arch/x86/cpu/amd.c
@@ -920,6 +920,13 @@ void amd_init_de_cfg(const struct cpuinfo_x86 *c)
     if ( zenbleed_use_chickenbit() )
         new |= (1 << 9);
 
+    /*
+     * Erratum #665, doc 44739.  Integer divide instructions may cause
+     * unpredictable behaviour.
+     */
+    if ( c->family == 0x12 )
+        new |= 1U << 31;
+
     /* Avoid reading DE_CFG if we don't intend to change anything. */
     if ( !new )
         return;
@@ -1201,15 +1208,6 @@ static void cf_check init_amd(struct cpuinfo_x86 *c)
                                            smp_processor_id());
                        wrmsrl(MSR_AMD64_LS_CFG, value | (1 << 15));
                }
-       } else if (c->x86 == 0x12) {
-               rdmsrl(MSR_AMD64_DE_CFG, value);
-               if (!(value & (1U << 31))) {
-                       if (c == &boot_cpu_data || opt_cpu_info)
-                               printk_once(XENLOG_WARNING
-                                           "CPU%u: Applying workaround for 
erratum 665\n",
-                                           smp_processor_id());
-                       wrmsrl(MSR_AMD64_DE_CFG, value | (1U << 31));
-               }
        }
 
        /* AMD CPUs do not support SYSENTER outside of legacy mode. */
-- 
2.39.5