On 05.12.2025 13:33, Andrew Cooper wrote:
> On 24/11/2025 3:02 pm, Jan Beulich wrote:
>> EVEX.W meaning is unusual for VBMAC{,X}OR16x16x16, but that needs taking
>> care of only in the test harness.
>>
>> Like already proposed in "x86emul: support AVX10.1", use just
>> vcpu_must_have(), not host_and_vcpu_must_have().
>>
>> Signed-off-by: Jan Beulich <[email protected]>
>> ---
>> The Disp8Shift settings are guesswork; the binutils submission bogusly(?)
>> suggests no scaling at all.I realize I should have dropped this remark: It was applicable only to early versions of that change. >> No idea how to test this without having access to capable hardware. AMD, >> to my knowledge, offers no equivalent to Intel's SDE. > > I'm not aware of anything equivalent for AMD. > > IIRC, the binutils thread says Zen6 for these instructions? I'm still > trying to get access myself. No ETA yet. Yes, that's what they add for Zen6. I committed that patch just earlier today. > Very tentatively Acked-by: Andrew Cooper <[email protected]> Thanks. I'll put this into the patch as-is; it's unclear to me though whether I could legitimately commit the patch with this. (It really doesn't depend on earlier patches in the series, after all.) > Given that .W is wonky for these instructions, I wouldn't quite so > easily rule out other wonkyness. It's AMD's way of giving .W dual purpose; really triple now. > Would the test harness pick that up? Not AFAICT. Not without adding something to it, which I think makes sense only when one can test it. (Which is where Intel's SDE helps quite a bit.) Jan
