Use U where necessary (Misra Rule 7.2) and uppercase L (Misra Rule 7.3). No functional change.
Signed-off-by: Andrew Cooper <[email protected]> --- CC: Jan Beulich <[email protected]> CC: Roger Pau Monné <[email protected]> CC: Stefano Stabellini <[email protected]> CC: Julien Grall <[email protected]> CC: Volodymyr Babchuk <[email protected]> CC: Bertrand Marquis <[email protected]> CC: Michal Orzel <[email protected]> CC: [email protected] <[email protected]> CC: Nicola Vetrini <[email protected]> --- xen/arch/arm/gic-v3-its.c | 2 +- xen/arch/arm/include/asm/tee/optee_msg.h | 16 ++++++++-------- xen/arch/arm/include/asm/tee/optee_smc.h | 8 ++++---- xen/arch/arm/tee/optee.c | 6 +++--- xen/arch/x86/guest/xen/xen.c | 2 +- xen/arch/x86/include/asm/config.h | 2 +- xen/arch/x86/include/asm/guest/hyperv.h | 2 +- xen/arch/x86/pv/emul-gate-op.c | 2 +- xen/arch/x86/tboot.c | 4 ++-- xen/drivers/char/xhci-dbc.c | 14 +++++++------- 10 files changed, 29 insertions(+), 29 deletions(-) diff --git a/xen/arch/arm/gic-v3-its.c b/xen/arch/arm/gic-v3-its.c index 34833166adcc..9ba068c46fcb 100644 --- a/xen/arch/arm/gic-v3-its.c +++ b/xen/arch/arm/gic-v3-its.c @@ -76,7 +76,7 @@ static const struct its_quirk its_quirks[] = { { .desc = "R-Car Gen4", .iidr = 0x0201743b, - .mask = 0xffffffff, + .mask = 0xffffffffU, .init = gicv3_its_enable_quirk_gen4, }, { diff --git a/xen/arch/arm/include/asm/tee/optee_msg.h b/xen/arch/arm/include/asm/tee/optee_msg.h index fe743dbde3c8..09820ff8638c 100644 --- a/xen/arch/arm/include/asm/tee/optee_msg.h +++ b/xen/arch/arm/include/asm/tee/optee_msg.h @@ -222,10 +222,10 @@ struct optee_msg_arg { * Represented in 4 32-bit words in OPTEE_MSG_UID_0, OPTEE_MSG_UID_1, * OPTEE_MSG_UID_2, OPTEE_MSG_UID_3. */ -#define OPTEE_MSG_UID_0 0x384fb3e0 -#define OPTEE_MSG_UID_1 0xe7f811e3 -#define OPTEE_MSG_UID_2 0xaf630002 -#define OPTEE_MSG_UID_3 0xa5d5c51b +#define OPTEE_MSG_UID_0 0x384fb3e0U +#define OPTEE_MSG_UID_1 0xe7f811e3U +#define OPTEE_MSG_UID_2 0xaf630002U +#define OPTEE_MSG_UID_3 0xa5d5c51bU #define OPTEE_MSG_FUNCID_CALLS_UID 0xFF01 /* @@ -246,10 +246,10 @@ struct optee_msg_arg { * Returns UUID in 4 32-bit words in the same way as * OPTEE_MSG_FUNCID_CALLS_UID described above. */ -#define OPTEE_MSG_OS_OPTEE_UUID_0 0x486178e0 -#define OPTEE_MSG_OS_OPTEE_UUID_1 0xe7f811e3 -#define OPTEE_MSG_OS_OPTEE_UUID_2 0xbc5e0002 -#define OPTEE_MSG_OS_OPTEE_UUID_3 0xa5d5c51b +#define OPTEE_MSG_OS_OPTEE_UUID_0 0x486178e0U +#define OPTEE_MSG_OS_OPTEE_UUID_1 0xe7f811e3U +#define OPTEE_MSG_OS_OPTEE_UUID_2 0xbc5e0002U +#define OPTEE_MSG_OS_OPTEE_UUID_3 0xa5d5c51bU #define OPTEE_MSG_FUNCID_GET_OS_UUID 0x0000 /* diff --git a/xen/arch/arm/include/asm/tee/optee_smc.h b/xen/arch/arm/include/asm/tee/optee_smc.h index 2f5c702326f7..39c04eb5ad1b 100644 --- a/xen/arch/arm/include/asm/tee/optee_smc.h +++ b/xen/arch/arm/include/asm/tee/optee_smc.h @@ -443,9 +443,9 @@ #define OPTEE_SMC_CALL_RETURN_FROM_RPC \ OPTEE_SMC_STD_CALL_VAL(OPTEE_SMC_FUNCID_RETURN_FROM_RPC) -#define OPTEE_SMC_RETURN_RPC_PREFIX_MASK 0xFFFF0000 -#define OPTEE_SMC_RETURN_RPC_PREFIX 0xFFFF0000 -#define OPTEE_SMC_RETURN_RPC_FUNC_MASK 0x0000FFFF +#define OPTEE_SMC_RETURN_RPC_PREFIX_MASK 0xFFFF0000U +#define OPTEE_SMC_RETURN_RPC_PREFIX 0xFFFF0000U +#define OPTEE_SMC_RETURN_RPC_FUNC_MASK 0x0000FFFFU #define OPTEE_SMC_RETURN_GET_RPC_FUNC(ret) \ ((ret) & OPTEE_SMC_RETURN_RPC_FUNC_MASK) @@ -548,7 +548,7 @@ OPTEE_SMC_RPC_VAL(OPTEE_SMC_RPC_FUNC_CMD) /* Returned in a0 */ -#define OPTEE_SMC_RETURN_UNKNOWN_FUNCTION 0xFFFFFFFF +#define OPTEE_SMC_RETURN_UNKNOWN_FUNCTION 0xFFFFFFFFU /* Returned in a0 only from Trusted OS functions */ #define OPTEE_SMC_RETURN_OK 0x0 diff --git a/xen/arch/arm/tee/optee.c b/xen/arch/arm/tee/optee.c index 5151bd90ed02..699e8d536862 100644 --- a/xen/arch/arm/tee/optee.c +++ b/xen/arch/arm/tee/optee.c @@ -49,16 +49,16 @@ #define TEEC_ORIGIN_COMMS 0x00000002 /* "Non-specific cause" as in GP TEE Client API Specification */ -#define TEEC_ERROR_GENERIC 0xFFFF0000 +#define TEEC_ERROR_GENERIC 0xFFFF0000U /* * "Input parameters were invalid" as described * in GP TEE Client API Specification. */ -#define TEEC_ERROR_BAD_PARAMETERS 0xFFFF0006 +#define TEEC_ERROR_BAD_PARAMETERS 0xFFFF0006U /* "System ran out of resources" as in GP TEE Client API Specification */ -#define TEEC_ERROR_OUT_OF_MEMORY 0xFFFF000C +#define TEEC_ERROR_OUT_OF_MEMORY 0xFFFF000CU /* Client ID 0 is reserved for the hypervisor itself */ #define OPTEE_CLIENT_ID(domain) ((domain)->domain_id + 1) diff --git a/xen/arch/x86/guest/xen/xen.c b/xen/arch/x86/guest/xen/xen.c index 77a3a8742a3e..315e5ded05ab 100644 --- a/xen/arch/x86/guest/xen/xen.c +++ b/xen/arch/x86/guest/xen/xen.c @@ -120,7 +120,7 @@ static void map_shared_info(void) /* Mask all upcalls */ for ( i = 0; i < ARRAY_SIZE(XEN_shared_info->evtchn_mask); i++ ) - write_atomic(&XEN_shared_info->evtchn_mask[i], ~0ul); + write_atomic(&XEN_shared_info->evtchn_mask[i], ~0UL); } static int map_vcpuinfo(void) diff --git a/xen/arch/x86/include/asm/config.h b/xen/arch/x86/include/asm/config.h index cc80f2c62310..1b28349a427b 100644 --- a/xen/arch/x86/include/asm/config.h +++ b/xen/arch/x86/include/asm/config.h @@ -200,7 +200,7 @@ #ifdef CONFIG_PV32 /* This is not a fixed value, just a lower limit. */ -#define __HYPERVISOR_COMPAT_VIRT_START 0xF5800000 +#define __HYPERVISOR_COMPAT_VIRT_START 0xF5800000U #define HYPERVISOR_COMPAT_VIRT_START(d) ((d)->arch.pv.hv_compat_vstart) #else /* !CONFIG_PV32 */ diff --git a/xen/arch/x86/include/asm/guest/hyperv.h b/xen/arch/x86/include/asm/guest/hyperv.h index c05efdce71a4..dabc62727b44 100644 --- a/xen/arch/x86/include/asm/guest/hyperv.h +++ b/xen/arch/x86/include/asm/guest/hyperv.h @@ -11,7 +11,7 @@ #include <xen/types.h> /* Use top-most MFN for hypercall page */ -#define HV_HCALL_MFN (((1ull << paddr_bits) - 1) >> HV_HYP_PAGE_SHIFT) +#define HV_HCALL_MFN (((1ULL << paddr_bits) - 1) >> HV_HYP_PAGE_SHIFT) /* * The specification says: "The partition reference time is computed diff --git a/xen/arch/x86/pv/emul-gate-op.c b/xen/arch/x86/pv/emul-gate-op.c index dcac0a04015b..1faf13b962b1 100644 --- a/xen/arch/x86/pv/emul-gate-op.c +++ b/xen/arch/x86/pv/emul-gate-op.c @@ -32,7 +32,7 @@ static int read_gate_descriptor(unsigned int gate_sel, return 0; *sel = (desc.a >> 16) & 0x0000fffc; - *off = (desc.a & 0x0000ffff) | (desc.b & 0xffff0000); + *off = (desc.a & 0x0000ffff) | (desc.b & 0xffff0000U); *ar = desc.b & 0x0000ffff; /* diff --git a/xen/arch/x86/tboot.c b/xen/arch/x86/tboot.c index 9d9bb6e7cf6d..0b3d596690cc 100644 --- a/xen/arch/x86/tboot.c +++ b/xen/arch/x86/tboot.c @@ -41,8 +41,8 @@ static bool __ro_after_init is_vtd; * TXT configuration registers (offsets from TXT_{PUB, PRIV}_CONFIG_REGS_BASE) */ -#define TXT_PUB_CONFIG_REGS_BASE 0xfed30000 -#define TXT_PRIV_CONFIG_REGS_BASE 0xfed20000 +#define TXT_PUB_CONFIG_REGS_BASE 0xfed30000U +#define TXT_PRIV_CONFIG_REGS_BASE 0xfed20000U /* # pages for each config regs space - used by fixmap */ #define NR_TXT_CONFIG_PAGES ((TXT_PUB_CONFIG_REGS_BASE - \ diff --git a/xen/drivers/char/xhci-dbc.c b/xen/drivers/char/xhci-dbc.c index 1f7d4395dc9d..c1ff528de62f 100644 --- a/xen/drivers/char/xhci-dbc.c +++ b/xen/drivers/char/xhci-dbc.c @@ -353,8 +353,8 @@ static bool __init dbc_init_xhc(struct dbc *dbc) cmd = pci_conf_read16(dbc->sbdf, PCI_COMMAND); pci_conf_write16(dbc->sbdf, PCI_COMMAND, cmd & ~PCI_COMMAND_MEMORY); - pci_conf_write32(dbc->sbdf, PCI_BASE_ADDRESS_0, 0xFFFFFFFF); - pci_conf_write32(dbc->sbdf, PCI_BASE_ADDRESS_1, 0xFFFFFFFF); + pci_conf_write32(dbc->sbdf, PCI_BASE_ADDRESS_0, 0xFFFFFFFFU); + pci_conf_write32(dbc->sbdf, PCI_BASE_ADDRESS_1, 0xFFFFFFFFU); bar_size = pci_conf_read32(dbc->sbdf, PCI_BASE_ADDRESS_0); bar_size |= (uint64_t)pci_conf_read32(dbc->sbdf, PCI_BASE_ADDRESS_1) << 32; xhc_mmio_size = ~(bar_size & PCI_BASE_ADDRESS_MEM_MASK) + 1; @@ -398,7 +398,7 @@ static struct dbc_reg __iomem *xhci_find_dbc(struct dbc *dbc) * This is initially an offset to the first capability. All the offsets * (both in HCCP1 and then next capability pointer) are dword-based. */ - next = (readl(hccp1) & 0xFFFF0000) >> 16; + next = readl(hccp1) >> 16; while ( id != DBC_ID && next && ttl-- ) { @@ -735,7 +735,7 @@ static void dbc_init_ep(uint32_t *ep, uint64_t mbs, uint32_t type, memset(ep, 0, DBC_CTX_BYTES); ep[1] = (1024 << 16) | ((uint32_t)mbs << 8) | (type << 3); - ep[2] = (ring_dma & 0xFFFFFFFF) | 1; + ep[2] = (uint32_t)ring_dma | 1; ep[3] = ring_dma >> 32; ep[4] = 3 * 1024; } @@ -816,7 +816,7 @@ static void dbc_reset_debug_port(struct dbc *dbc) * This is initially an offset to the first capability. All the offsets * (both in HCCP1 and then next capability pointer are dword-based. */ - next = (readl(hccp1) & 0xFFFF0000) >> 16; + next = readl(hccp1) >> 16; /* * Look for "supported protocol" capability, major revision 3. @@ -1094,7 +1094,7 @@ static void dbc_enqueue_in(struct dbc *dbc, struct xhci_trb_ring *trb, struct dbc_work_ring *wrk) { struct dbc_reg *reg = dbc->dbc_reg; - uint32_t db = (readl(®->db) & 0xFFFF00FF) | (trb->db << 8); + uint32_t db = (readl(®->db) & 0xFFFF00FFU) | (trb->db << 8); /* Check if there is already queued TRB */ if ( xhci_trb_ring_size(trb) >= 1 ) @@ -1289,7 +1289,7 @@ static void cf_check dbc_uart_resume(struct serial_port *port) struct dbc_uart *uart = port->uart; struct dbc *dbc = &uart->dbc; - pci_conf_write32(dbc->sbdf, PCI_BASE_ADDRESS_0, dbc->bar_val & 0xFFFFFFFF); + pci_conf_write32(dbc->sbdf, PCI_BASE_ADDRESS_0, dbc->bar_val); pci_conf_write32(dbc->sbdf, PCI_BASE_ADDRESS_1, dbc->bar_val >> 32); pci_conf_write16(dbc->sbdf, PCI_COMMAND, dbc->pci_cr); -- 2.39.5
