The L2H, L3, and L4 forms only have GUEST_PAGING_LEVELS=4 call sites, i.e. their 2- and 3-level forms are unreachable, violating Misra rule 2.1. The L2H form additionally is unused (call site DCE-d) with PV32=n.
Signed-off-by: Jan Beulich <[email protected]> --- a/xen/arch/x86/mm/shadow/multi.c +++ b/xen/arch/x86/mm/shadow/multi.c @@ -1789,35 +1789,30 @@ sh_map_and_validate(struct vcpu *v, mfn_ return result; } +#if GUEST_PAGING_LEVELS >= 4 int sh_map_and_validate_gl4e(struct vcpu *v, mfn_t gl4mfn, void *new_gl4p, u32 size) { -#if GUEST_PAGING_LEVELS >= 4 return sh_map_and_validate(v, gl4mfn, new_gl4p, size, SH_type_l4_shadow, shadow_l4_index, validate_gl4e); -#else // ! GUEST_PAGING_LEVELS >= 4 - BUG(); /* Called in wrong paging mode! */ -#endif } int sh_map_and_validate_gl3e(struct vcpu *v, mfn_t gl3mfn, void *new_gl3p, u32 size) { -#if GUEST_PAGING_LEVELS >= 4 return sh_map_and_validate(v, gl3mfn, new_gl3p, size, SH_type_l3_shadow, shadow_l3_index, validate_gl3e); -#else // ! GUEST_PAGING_LEVELS >= 4 - BUG(); /* Called in wrong paging mode! */ -#endif } +#endif /* GUEST_PAGING_LEVELS >= 4 */ + int sh_map_and_validate_gl2e(struct vcpu *v, mfn_t gl2mfn, void *new_gl2p, u32 size) @@ -1828,19 +1823,17 @@ sh_map_and_validate_gl2e(struct vcpu *v, validate_gl2e); } +#if defined(CONFIG_PV32) && GUEST_PAGING_LEVELS >= 4 int sh_map_and_validate_gl2he(struct vcpu *v, mfn_t gl2mfn, void *new_gl2p, u32 size) { -#if GUEST_PAGING_LEVELS >= 4 && defined(CONFIG_PV32) return sh_map_and_validate(v, gl2mfn, new_gl2p, size, SH_type_l2h_shadow, shadow_l2_index, validate_gl2e); -#else /* Non-PAE guests don't have different kinds of l2 table */ - BUG(); /* Called in wrong paging mode! */ -#endif } +#endif /* CONFIG_PV32 && GUEST_PAGING_LEVELS >= 4 */ int sh_map_and_validate_gl1e(struct vcpu *v, mfn_t gl1mfn,
