On 26/10/18 10:03, Jan Beulich wrote: >>>> On 25.10.18 at 20:32, <[email protected]> wrote: >> On 18/09/18 12:53, Jan Beulich wrote: >>> @@ -1187,6 +1188,11 @@ static int _get_fpu( >>> return X86EMUL_UNHANDLEABLE; >>> break; >>> >>> + case X86EMUL_FPU_opmask: >>> + if ( !(xcr0 & X86_XCR0_SSE) || !(xcr0 & X86_XCR0_OPMASK) ) >>> + return X86EMUL_UNHANDLEABLE; >>> + break; >> I see this follows the pattern from X86EMUL_FPU_ymm, but by the SSE >> check? It is not relevant at this point - if xcr0.opmask is set, the >> opmask instructions should be usable. > I would agree with you from a functional POV, but please see the > last row of the table named "OS XSAVE Enabling Requirements of > Instruction Categories" in SDM Vol 2.
Hmm. That table is in contradiction to Vol 3 Figure 2-8 and associated description, which enumerates the #GP conditions of XSETBV. In particular, it suggests that OPMASK must be set in union with the ZMM bits, and cannot be set without YMM. IMO, we can require/expect get_xcr0() to pass an architecturally valid result. I don't think we should be checking the transitive closure of feature dependences here. ~Andrew _______________________________________________ Xen-devel mailing list [email protected] https://lists.xenproject.org/mailman/listinfo/xen-devel
