On 03/12/2018 16:24, Jan Beulich wrote: >>>> On 03.12.18 at 17:18, <andrew.coop...@citrix.com> wrote: >> This is a lingering TODO item from XSA-263. It adds support AMD's >> MSR_VIRT_SPEC_CTRL interface, and changes Xen's "boot time global" SSBD >> setting into a per-vcpu setting. >> >> This can be found on: >> git://xenbits.xen.org/people/andrewcoop/xen.git xen-virt-spec-ctrl-v1 >> >> The start of the series is some cleanup. It then teaches Xen to recognise >> the >> available interfaces (including MSR_VIRT_SPEC_CTRL from a hypervisor), then >> how to safely context switch the per-core LS_CFG on Fam17h, an finally to >> expose support to guests. >> >> I've got some further MSR work coming because we have to fix the >> default-leakiness of MSRs in this range, because a guest becomes unsafe to >> migrate as soon as it reads any of the pipeline control MSRs. > I've seen you mention this elsewhere, but I'm still unclear about > the "why" part here.
Because the existence (or not) are model specific, the details read are non-architectural, not always the same on minor variations of the same platform, and definitely not the same across different models. I'm lead to believe that is only blind luck that the LFENCE serialising bit in DE_CFG is in the same position on all currently applicable hardware, and there are no plans to make this architectural. ~Andrew _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel
