From: Andrii Anisov <andrii_ani...@epam.com>
This action is excessive because for an invalid LR there is no need
to write another invalid value to a register. So we can skip it here,
saving a peripheral register write.
Keep clearing the LR for the DEBUG build. This would make dumped
invalid LRs be zero. That is more obvious than picking state bits
from a non-zero value.
Signed-off-by: Andrii Anisov <andrii_ani...@epam.com>
Reviewed-by: Julien Grall <julien.gr...@arm.com>
---
xen/arch/arm/gic-vgic.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/xen/arch/arm/gic-vgic.c b/xen/arch/arm/gic-vgic.c
index 990399c..48922f5 100644
--- a/xen/arch/arm/gic-vgic.c
+++ b/xen/arch/arm/gic-vgic.c
@@ -216,7 +216,9 @@ static void gic_update_one_lr(struct vcpu *v, int i)
}
else
{
+#ifndef NDEBUG
gic_hw_ops->clear_lr(i);
+#endif
clear_bit(i, &this_cpu(lr_mask));
if ( p->desc != NULL )
--
2.7.4
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