The Hygon Dhyana CPU supports lots of MSRs(such as perf event select and
counter MSRs, hardware configuration MSR, MMIO configuration base address
MSR, MPERF/APERF MSRs) as AMD CPU does, so add Hygon Dhyana support to the
PV emulation infrastructure by using the code path of AMD.
As hygon.c needs to write the load-store configuration(LS_CFG) MSR, so add
new case in write_msr to handle this situation.
Signed-off-by: Pu Wen <pu...@hygon.cn>
---
xen/arch/x86/pv/emul-priv-op.c | 29 ++++++++++++++++++++++++-----
1 file changed, 24 insertions(+), 5 deletions(-)
diff --git a/xen/arch/x86/pv/emul-priv-op.c b/xen/arch/x86/pv/emul-priv-op.c
index a84f3f1..936178e 100644
--- a/xen/arch/x86/pv/emul-priv-op.c
+++ b/xen/arch/x86/pv/emul-priv-op.c
@@ -927,7 +927,9 @@ static int read_msr(unsigned int reg, uint64_t *val,
/* fall through */
case MSR_AMD_FAM15H_EVNTSEL0 ... MSR_AMD_FAM15H_PERFCTR5:
case MSR_K7_EVNTSEL0 ... MSR_K7_PERFCTR3:
- if ( vpmu_msr || (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) )
+ if ( vpmu_msr ||
+ (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) ||
+ (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) )
{
if ( vpmu_do_rdmsr(reg, val) )
break;
@@ -1009,7 +1011,8 @@ static int write_msr(unsigned int reg, uint64_t val,
case MSR_K8_PSTATE6:
case MSR_K8_PSTATE7:
case MSR_K8_HWCR:
- if ( boot_cpu_data.x86_vendor != X86_VENDOR_AMD )
+ if ( boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
+ boot_cpu_data.x86_vendor != X86_VENDOR_HYGON )
break;
if ( likely(!is_cpufreq_controller(currd)) ||
wrmsr_safe(reg, val) == 0 )
@@ -1029,9 +1032,22 @@ static int write_msr(unsigned int reg, uint64_t val,
return X86EMUL_OKAY;
break;
+ case MSR_AMD64_LS_CFG:
+ if ( boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
+ boot_cpu_data.x86_vendor != X86_VENDOR_HYGON )
+ break;
+ if ( !is_hardware_domain(currd) || !is_pinned_vcpu(curr) )
+ return X86EMUL_OKAY;
+ if ( is_pv_32bit_domain(currd) || !is_canonical_address(val) )
+ break;
+ if ( wrmsr_safe(reg, val) == 0 )
+ return X86EMUL_OKAY;
+ break;
+
case MSR_FAM10H_MMIO_CONF_BASE:
- if ( boot_cpu_data.x86_vendor != X86_VENDOR_AMD ||
- boot_cpu_data.x86 < 0x10 || boot_cpu_data.x86 > 0x17 )
+ if ( (boot_cpu_data.x86_vendor != X86_VENDOR_AMD ||
+ boot_cpu_data.x86 < 0x10 || boot_cpu_data.x86 > 0x17) &&
+ boot_cpu_data.x86_vendor != X86_VENDOR_HYGON )
break;
if ( !is_hardware_domain(currd) || !is_pinned_vcpu(curr) )
return X86EMUL_OKAY;
@@ -1070,6 +1086,7 @@ static int write_msr(unsigned int reg, uint64_t val,
case MSR_IA32_MPERF:
case MSR_IA32_APERF:
if ( (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) &&
+ (boot_cpu_data.x86_vendor != X86_VENDOR_HYGON) &&
(boot_cpu_data.x86_vendor != X86_VENDOR_AMD) )
break;
if ( likely(!is_cpufreq_controller(currd)) ||
@@ -1103,7 +1120,9 @@ static int write_msr(unsigned int reg, uint64_t val,
vpmu_msr = true;
case MSR_AMD_FAM15H_EVNTSEL0 ... MSR_AMD_FAM15H_PERFCTR5:
case MSR_K7_EVNTSEL0 ... MSR_K7_PERFCTR3:
- if ( vpmu_msr || (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) )
+ if ( vpmu_msr ||
+ (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) ||
+ (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) )
{
if ( (vpmu_mode & XENPMU_MODE_ALL) &&
!is_hardware_domain(currd) )
--
2.7.4
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