On 30/03/2019 10:40, Pu Wen wrote:
> As a new x86 CPU vendor, Chengdu Haiguang IC Design Co., Ltd (Hygon)
> is a joint venture between AMD and Haiguang Information Technology Co.,
> Ltd., aims at providing high performance x86 processors for China
> server market.
>
> The first generation Hygon processor(Dhyana) originates from AMD
> technology and shares most of the architecture with AMD's family 17h,
> but with different CPU vendor ID("HygonGenuine") and family series
> number 18h (Hygon negotiated with AMD to make sure that only Hygon
> will use family 18h).
>
> To enable support of Xen to Hygon Dhyana CPU, add a new vendor type
> (X86_VENDOR_HYGON, with value of 5), and share most of the code with
> AMD family 17h.
>
> The MSRs and CPUIDs which are used by this patch series are all defined
> in this PPR[1].
>
> This patch series have been applied and tested successfully on Hygon
> Dhyana processor, also been tested on AMD EPYC (family 17h) processor.
> It works fine and makes no harm to the existing code.
>
> Reference:
> [1]
> https://www.amd.com/system/files/TechDocs/54945_PPR_Family_17h_Models_00h-0Fh.pdf
One thing I don't see in this series is anything about microcode
loading. Presumably you'll follow the AMD patchloading mechanism, with
a blob you provide yourself?
~Andrew
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