The Hygon Dhyana CPU supports lots of MSRs(such as perf event select and counter MSRs, hardware configuration MSR, MMIO configuration base address MSR, MPERF/APERF MSRs) as AMD CPU does, so add Hygon Dhyana support to the PV emulation infrastructure by using the code path of AMD.
Signed-off-by: Pu Wen <pu...@hygon.cn> Acked-by: Jan Beulich <jbeul...@suse.com> --- xen/arch/x86/pv/emul-priv-op.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/xen/arch/x86/pv/emul-priv-op.c b/xen/arch/x86/pv/emul-priv-op.c index 84ce67c..4f73375 100644 --- a/xen/arch/x86/pv/emul-priv-op.c +++ b/xen/arch/x86/pv/emul-priv-op.c @@ -924,7 +924,9 @@ static int read_msr(unsigned int reg, uint64_t *val, /* fall through */ case MSR_AMD_FAM15H_EVNTSEL0 ... MSR_AMD_FAM15H_PERFCTR5: case MSR_K7_EVNTSEL0 ... MSR_K7_PERFCTR3: - if ( vpmu_msr || (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) ) + if ( vpmu_msr || + (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) || + (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) ) { if ( vpmu_do_rdmsr(reg, val) ) break; @@ -1006,7 +1008,8 @@ static int write_msr(unsigned int reg, uint64_t val, case MSR_K8_PSTATE6: case MSR_K8_PSTATE7: case MSR_K8_HWCR: - if ( boot_cpu_data.x86_vendor != X86_VENDOR_AMD ) + if ( boot_cpu_data.x86_vendor != X86_VENDOR_AMD && + boot_cpu_data.x86_vendor != X86_VENDOR_HYGON ) break; if ( likely(!is_cpufreq_controller(currd)) || wrmsr_safe(reg, val) == 0 ) @@ -1027,8 +1030,9 @@ static int write_msr(unsigned int reg, uint64_t val, break; case MSR_FAM10H_MMIO_CONF_BASE: - if ( boot_cpu_data.x86_vendor != X86_VENDOR_AMD || - boot_cpu_data.x86 < 0x10 || boot_cpu_data.x86 > 0x17 ) + if ( (boot_cpu_data.x86_vendor != X86_VENDOR_AMD || + boot_cpu_data.x86 < 0x10 || boot_cpu_data.x86 > 0x17) && + boot_cpu_data.x86_vendor != X86_VENDOR_HYGON ) break; if ( !is_hwdom_pinned_vcpu(curr) ) return X86EMUL_OKAY; @@ -1067,7 +1071,8 @@ static int write_msr(unsigned int reg, uint64_t val, case MSR_IA32_MPERF: case MSR_IA32_APERF: if ( (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) && - (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) ) + (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) && + (boot_cpu_data.x86_vendor != X86_VENDOR_HYGON) ) break; if ( likely(!is_cpufreq_controller(currd)) || wrmsr_safe(reg, val) == 0 ) @@ -1099,7 +1104,9 @@ static int write_msr(unsigned int reg, uint64_t val, vpmu_msr = true; case MSR_AMD_FAM15H_EVNTSEL0 ... MSR_AMD_FAM15H_PERFCTR5: case MSR_K7_EVNTSEL0 ... MSR_K7_PERFCTR3: - if ( vpmu_msr || (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) ) + if ( vpmu_msr || + (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) || + (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) ) { if ( (vpmu_mode & XENPMU_MODE_ALL) && !is_hardware_domain(currd) ) -- 2.7.4 _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel