On 15/03/2019 10:55, Jan Beulich wrote:
> Also include the only other AVX512ER insn pair, VEXP2P{D,S}.
>
> Note that despite the replacement of the SHA insns' table slots there's
> no need to special case their decoding: Their insn-specific code already
> sets op_bytes (as was required due to simd_other), and TwoOp is of no
> relevance for legacy encoded SIMD insns.
>
> The raising of #UD when EVEX.L'L is 3 for AVX512ER scalar insns is done
> to be on the safe side. The SDM does not clarify behavior there, and
> it's even more ambiguous here (without AVX512VL in the picture).
>
> Signed-off-by: Jan Beulich <jbeul...@suse.com>Acked-by: Andrew Cooper <andrew.coop...@citrix.com> Seeing as I have some ER hardware, is there an easy way to get GCC/binutils to emit a weird L'L field, or will this involve some manual opcode generation to test? ~Andrew _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel
