On Fri, Jun 05, 2020 at 10:10:01AM +0200, Jan Beulich wrote: > On 05.06.2020 10:02, Roger Pau Monné wrote: > > On Fri, Jun 05, 2020 at 09:51:09AM +0200, Jan Beulich wrote: > >> Both match prior generation processors as far as LBR and C-state MSRs > >> go (SDM rev 072) as well as applicability of the if_pschange_mc erratum > >> (recent spec updates). > >> > >> Signed-off-by: Jan Beulich <jbeul...@suse.com> > >> --- > >> Such changes having been subject to backporting in the past, this > >> change may want considering for 4.14. > >> --- > >> I'm leaving alone spec_ctrl.c, albeit there's a scary looking erratum > >> for Ice Lake indicating that MDS_NO may wrongly be set. But this is > >> apparently addressed by ucode update, so we may not need to deal with > >> it in software. > >> > >> --- a/xen/arch/x86/acpi/cpu_idle.c > >> +++ b/xen/arch/x86/acpi/cpu_idle.c > > > > What about mwait-idle? I guess we pick that from Linux and no patch > > has been added so far? > > Correct. I've looked at recent history there, and I'm uncertain they'll > add further models there. They look to prefer to use ACPI _CST now again > with, as it seems, not overly much of a difference to the ACPI driver > (which, if we were to follow, I'd rather see us integrate there).
Urg, OK, that's a shame as using mwait-idle was IMO better from a Xen PoV as we didn't rely on dom0 in order to discover C states. I wonder if we could continue to update mwait-idle on our own for newer models. FWIW, wikichip also lists 6c and 6a [0] as Ice Lake Server model versions, but I'm not sure if this has been confirmed in any way? Roger. [0] https://en.wikichip.org/wiki/intel/cpuid#Big_Cores_.28Server.29
