Hi Julien, > -----Original Message----- > From: Julien Grall <jul...@xen.org> > Sent: 2020年8月18日 17:51 > To: Wei Chen <wei.c...@arm.com>; xen-devel@lists.xenproject.org; > sstabell...@kernel.org > Cc: Andre Przywara <andre.przyw...@arm.com>; Bertrand Marquis > <bertrand.marq...@arm.com>; Steve Capper <steve.cap...@arm.com>; > Kaly Xin <kaly....@arm.com> > Subject: Re: [PATCH] xen/arm: Missing N1/A76/A75 FP registers in vCPU > context switch > > Hi Wei, > > On 18/08/2020 04:11, Wei Chen wrote: > > Xen has cpu_has_fp/cpu_has_simd to detect whether the CPU supports > > FP/SIMD or not. But currently, this two MACROs only consider value 0 > > s/this/these/
Got it > > > of ID_AA64PFR0_EL1.FP/SIMD as FP/SIMD features enabled. But for CPUs > > that support FP/SIMD and half-precision floating-point features, the > > ID_AA64PFR0_EL1.FP/SIMD are 1. For these CPUs, xen will treat them as > > no FP/SIMD support. In this case, the vfp_save/restore_state will not > > take effect. > > > > Unfortunately, Cortex-N1/A76/A75 are the CPUs support FP/SIMD and > > half-precision floatiing-point. > > I am not sure to understand this sentence. Could you clarify? > Sorry about my unclear express. From the TRM documents (Cortex-A75/A76/N1), I found their ID_AA64PFR0_EL1.FP and ID_AA64PFR0_EL1.SIMD fields are 0x1. It's because except basic Advanced SIMD/FP supports, these CPUs also support half-precision floating-point arithmetic. > > Their ID_AA64PFR0_EL1.FP/SMID are 1 > > (see Arm ARM DDI0487F.b, D13.2.64). In this case, on N1/A76/A75 > > platforms, Xen will always miss the float pointer registers save/restore. > > s/float pointer/floating point/? > Yes > > If different vCPUs are running on the same pCPU, the float pointer > > Likewise? > Yes, I will fix these typos in next version. > > registers will be corrupted randomly. > > > > This patch fixes Xen on these new cores. > > > > Signed-off-by: Wei Chen <wei.c...@arm.com> > > --- > > xen/include/asm-arm/cpufeature.h | 4 ++-- > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > diff --git a/xen/include/asm-arm/cpufeature.h b/xen/include/asm- > arm/cpufeature.h > > index 674beb0353..588089e5ae 100644 > > --- a/xen/include/asm-arm/cpufeature.h > > +++ b/xen/include/asm-arm/cpufeature.h > > @@ -13,8 +13,8 @@ > > #define cpu_has_el2_64 (boot_cpu_feature64(el2) >= 1) > > #define cpu_has_el3_32 (boot_cpu_feature64(el3) == 2) > > #define cpu_has_el3_64 (boot_cpu_feature64(el3) >= 1) > > -#define cpu_has_fp (boot_cpu_feature64(fp) == 0) > > -#define cpu_has_simd (boot_cpu_feature64(simd) == 0) > > +#define cpu_has_fp (boot_cpu_feature64(fp) <= 1) > > +#define cpu_has_simd (boot_cpu_feature64(simd) <= 1) > > #define cpu_has_gicv3 (boot_cpu_feature64(gic) == 1) > > #endif > > > > -- > > 2.17.1 > > > > IMPORTANT NOTICE: The contents of this email and any attachments are > confidential and may also be privileged. If you are not the intended > recipient, > please notify the sender immediately and do not disclose the contents to any > other person, use it for any purpose, or store or copy the information in any > medium. Thank you. > > Please configure your e-mail client to remove the disclaimer. > Thanks for this reminder. I have done. > Cheers, > > -- > Julien Grall
