Hi, > -----Original Message----- > From: Julien Grall <jul...@xen.org> > Sent: 2020年8月24日 21:15 > To: Wei Chen <wei.c...@arm.com>; xen-devel@lists.xenproject.org; > sstabell...@kernel.org > Cc: Andre Przywara <andre.przyw...@arm.com>; Bertrand Marquis > <bertrand.marq...@arm.com>; Penny Zheng <penny.zh...@arm.com>; > Kaly Xin <kaly....@arm.com>; nd <n...@arm.com> > Subject: Re: [PATCH v2 1/2] xen/arm: Missing N1/A76/A75 FP registers in > vCPU context switch > > Hi, > > On 24/08/2020 04:28, Wei Chen wrote: > > Xen has cpu_has_fp/cpu_has_simd to detect whether the CPU supports > > FP/SIMD or not. But currently, these two MACROs only consider value 0 > > of ID_AA64PFR0_EL1.FP/SIMD as FP/SIMD features enabled. But for CPUs > > that support FP/SIMD and half-precision floating-point arithmetic, the > > ID_AA64PFR0_EL1.FP/SIMD are 1 (see Arm ARM DDI0487F.b, D13.2.64). > > For these CPUs, xen will treat them as no FP/SIMD supporti, the > > s/supporti/support/
I will fix this typo in next version. > > > vfp_save/restore_state will not take effect. > > > > From the TRM documents of Cortex-A75/A76/N1, we know these CPUs > support > > basic Advanced SIMD/FP and half-precision floating-point arithmetic. In > > this case, on N1/A76/A75 platforms, Xen will always miss the floating > > pointer registers save/restore. If different vCPUs are running on the > > same pCPU, the floating pointer registers will be corrupted randomly. > > > > This patch fixes Xen on these new cores. > > > > Signed-off-by: Wei Chen <wei.c...@arm.com> > > Reviewed-by: Bertrand Marquis <bertrand.marq...@arm.com> > > Reviewed-by: Julien Grall <jgr...@amazon.com> > > Cheers, > > > --- > > xen/include/asm-arm/cpufeature.h | 4 ++-- > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > diff --git a/xen/include/asm-arm/cpufeature.h b/xen/include/asm- > arm/cpufeature.h > > index 674beb0353..10878ead8a 100644 > > --- a/xen/include/asm-arm/cpufeature.h > > +++ b/xen/include/asm-arm/cpufeature.h > > @@ -13,8 +13,8 @@ > > #define cpu_has_el2_64 (boot_cpu_feature64(el2) >= 1) > > #define cpu_has_el3_32 (boot_cpu_feature64(el3) == 2) > > #define cpu_has_el3_64 (boot_cpu_feature64(el3) >= 1) > > -#define cpu_has_fp (boot_cpu_feature64(fp) == 0) > > -#define cpu_has_simd (boot_cpu_feature64(simd) == 0) > > +#define cpu_has_fp (boot_cpu_feature64(fp) < 8) > > +#define cpu_has_simd (boot_cpu_feature64(simd) < 8) > > #define cpu_has_gicv3 (boot_cpu_feature64(gic) == 1) > > #endif > > > > > > -- > Julien Grall
