staging was not impacted by XSA-351 at the time of release, due to c/s
322ec7c89f and 84e848fd7a which disallows read access by default.
Forward port the XSA-351 changes to make the code structure consistent between
4.14 and 4.15.
This removes logspew for guests probing for the RAPL interface.
Signed-off-by: Andrew Cooper <andrew.coop...@citrix.com>
---
CC: Jan Beulich <jbeul...@suse.com>
CC: Roger Pau Monné <roger....@citrix.com>
CC: Wei Liu <w...@xen.org>
CC: Boris Ostrovsky <boris.ostrov...@oracle.com>
CC: Ian Jackson <i...@xenproject.org>
Technically this breaks Solaris/turbostat insofar as you can no longer use
msr_relaxed to "fix" the guest. The subsequent patch will unbreak it
differently.
For 4.15. Restoring behaviour closer to 4.14, and prereq for a bugfix needing
backporting.
---
xen/arch/x86/msr.c | 19 +++++++++++++++++++
xen/include/asm-x86/msr-index.h | 39 +++++++++++++++++++++++++++++++++++++++
2 files changed, 58 insertions(+)
diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c
index c3a988bd11..5927b6811b 100644
--- a/xen/arch/x86/msr.c
+++ b/xen/arch/x86/msr.c
@@ -188,6 +188,13 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t
*val)
case MSR_TSX_CTRL:
case MSR_MCU_OPT_CTRL:
case MSR_RTIT_OUTPUT_BASE ... MSR_RTIT_ADDR_B(7):
+ case MSR_RAPL_POWER_UNIT:
+ case MSR_PKG_POWER_LIMIT ... MSR_PKG_POWER_INFO:
+ case MSR_DRAM_POWER_LIMIT ... MSR_DRAM_POWER_INFO:
+ case MSR_PP0_POWER_LIMIT ... MSR_PP0_POLICY:
+ case MSR_PP1_POWER_LIMIT ... MSR_PP1_POLICY:
+ case MSR_PLATFORM_ENERGY_COUNTER:
+ case MSR_PLATFORM_POWER_LIMIT:
case MSR_U_CET:
case MSR_S_CET:
case MSR_PL0_SSP ... MSR_INTERRUPT_SSP_TABLE:
@@ -195,6 +202,8 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t *val)
case MSR_AMD64_LWP_CBADDR:
case MSR_PPIN_CTL:
case MSR_PPIN:
+ case MSR_F15H_CU_POWER ... MSR_F15H_CU_MAX_POWER:
+ case MSR_AMD_RAPL_POWER_UNIT ... MSR_AMD_PKG_ENERGY_STATUS:
case MSR_AMD_PPIN_CTL:
case MSR_AMD_PPIN:
goto gp_fault;
@@ -412,6 +421,7 @@ int guest_wrmsr(struct vcpu *v, uint32_t msr, uint64_t val)
case MSR_INTEL_CORE_THREAD_COUNT:
case MSR_INTEL_PLATFORM_INFO:
case MSR_ARCH_CAPABILITIES:
+ case MSR_IA32_PERF_STATUS:
/* Not offered to guests. */
case MSR_TEST_CTRL:
@@ -419,6 +429,13 @@ int guest_wrmsr(struct vcpu *v, uint32_t msr, uint64_t val)
case MSR_TSX_CTRL:
case MSR_MCU_OPT_CTRL:
case MSR_RTIT_OUTPUT_BASE ... MSR_RTIT_ADDR_B(7):
+ case MSR_RAPL_POWER_UNIT:
+ case MSR_PKG_POWER_LIMIT ... MSR_PKG_POWER_INFO:
+ case MSR_DRAM_POWER_LIMIT ... MSR_DRAM_POWER_INFO:
+ case MSR_PP0_POWER_LIMIT ... MSR_PP0_POLICY:
+ case MSR_PP1_POWER_LIMIT ... MSR_PP1_POLICY:
+ case MSR_PLATFORM_ENERGY_COUNTER:
+ case MSR_PLATFORM_POWER_LIMIT:
case MSR_U_CET:
case MSR_S_CET:
case MSR_PL0_SSP ... MSR_INTERRUPT_SSP_TABLE:
@@ -426,6 +443,8 @@ int guest_wrmsr(struct vcpu *v, uint32_t msr, uint64_t val)
case MSR_AMD64_LWP_CBADDR:
case MSR_PPIN_CTL:
case MSR_PPIN:
+ case MSR_F15H_CU_POWER ... MSR_F15H_CU_MAX_POWER:
+ case MSR_AMD_RAPL_POWER_UNIT ... MSR_AMD_PKG_ENERGY_STATUS:
case MSR_AMD_PPIN_CTL:
case MSR_AMD_PPIN:
goto gp_fault;
diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h
index f2e34dd22b..49c1afdd22 100644
--- a/xen/include/asm-x86/msr-index.h
+++ b/xen/include/asm-x86/msr-index.h
@@ -101,6 +101,38 @@
#define MSR_RTIT_ADDR_A(n) (0x00000580 + (n) * 2)
#define MSR_RTIT_ADDR_B(n) (0x00000581 + (n) * 2)
+/*
+ * Intel Runtime Average Power Limiting (RAPL) interface. Power plane base
+ * addresses (MSR_*_POWER_LIMIT) are model specific, but have so-far been
+ * consistent since their introduction in SandyBridge.
+ *
+ * Offsets of functionality from the power plane base is architectural, but
+ * not all power planes support all functionality.
+ */
+#define MSR_RAPL_POWER_UNIT 0x00000606
+
+#define MSR_PKG_POWER_LIMIT 0x00000610
+#define MSR_PKG_ENERGY_STATUS 0x00000611
+#define MSR_PKG_PERF_STATUS 0x00000613
+#define MSR_PKG_POWER_INFO 0x00000614
+
+#define MSR_DRAM_POWER_LIMIT 0x00000618
+#define MSR_DRAM_ENERGY_STATUS 0x00000619
+#define MSR_DRAM_PERF_STATUS 0x0000061b
+#define MSR_DRAM_POWER_INFO 0x0000061c
+
+#define MSR_PP0_POWER_LIMIT 0x00000638
+#define MSR_PP0_ENERGY_STATUS 0x00000639
+#define MSR_PP0_POLICY 0x0000063a
+
+#define MSR_PP1_POWER_LIMIT 0x00000640
+#define MSR_PP1_ENERGY_STATUS 0x00000641
+#define MSR_PP1_POLICY 0x00000642
+
+/* Intel Platform-wide power interface. */
+#define MSR_PLATFORM_ENERGY_COUNTER 0x0000064d
+#define MSR_PLATFORM_POWER_LIMIT 0x0000065c
+
#define MSR_U_CET 0x000006a0
#define MSR_S_CET 0x000006a2
#define CET_SHSTK_EN (_AC(1, ULL) << 0)
@@ -116,10 +148,17 @@
#define PASID_PASID_MASK 0x000fffff
#define PASID_VALID (_AC(1, ULL) << 31)
+#define MSR_F15H_CU_POWER 0xc001007a
+#define MSR_F15H_CU_MAX_POWER 0xc001007b
+
#define MSR_K8_VM_CR 0xc0010114
#define VM_CR_INIT_REDIRECTION (_AC(1, ULL) << 1)
#define VM_CR_SVM_DISABLE (_AC(1, ULL) << 4)
+#define MSR_AMD_RAPL_POWER_UNIT 0xc0010299
+#define MSR_AMD_CORE_ENERGY_STATUS 0xc001029a
+#define MSR_AMD_PKG_ENERGY_STATUS 0xc001029b
+
/*
* Legacy MSR constants in need of cleanup. No new MSRs below this comment.
*/
--
2.11.0
