> From: Igor Druzhinin <[email protected]> > Sent: Thursday, April 15, 2021 6:04 PM > > LBR, C-state MSRs should correspond to Ice Lake desktop according to > SDM rev. 74 for both models. > > Ice Lake-SP is known to expose IF_PSCHANGE_MC_NO in > IA32_ARCH_CAPABILITIES MSR > (as advisory tells and Whitley SDP confirms) which means the erratum is > fixed > in hardware for that model and therefore it shouldn't be present in > has_if_pschange_mc list. Provisionally assume the same to be the case > for Ice Lake-D. > > Reviewed-by: Jan Beulich <[email protected]> > Signed-off-by: Igor Druzhinin <[email protected]>
Reviewed-by: Kevin Tian <[email protected]> > --- > No changes in v5. > > Changes in v4: > - now based on SDM update > - new LBR (0x1e0)does not seem to be exposed in the docs > > Changes in v3: > - Add Ice Lake-D model numbers > - Drop has_if_pschange_mc hunk following Tiger Lake related discussion > --- > xen/arch/x86/acpi/cpu_idle.c | 2 ++ > xen/arch/x86/hvm/vmx/vmx.c | 2 +- > 2 files changed, 3 insertions(+), 1 deletion(-) > > diff --git a/xen/arch/x86/acpi/cpu_idle.c b/xen/arch/x86/acpi/cpu_idle.c > index c092086..d788c8b 100644 > --- a/xen/arch/x86/acpi/cpu_idle.c > +++ b/xen/arch/x86/acpi/cpu_idle.c > @@ -181,6 +181,8 @@ static void do_get_hw_residencies(void *arg) > case 0x55: > case 0x5E: > /* Ice Lake */ > + case 0x6A: > + case 0x6C: > case 0x7D: > case 0x7E: > /* Tiger Lake */ > diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c > index 30c6a57..91cba19 100644 > --- a/xen/arch/x86/hvm/vmx/vmx.c > +++ b/xen/arch/x86/hvm/vmx/vmx.c > @@ -2990,7 +2990,7 @@ static const struct lbr_info > *last_branch_msr_get(void) > /* Goldmont Plus */ > case 0x7a: > /* Ice Lake */ > - case 0x7d: case 0x7e: > + case 0x6a: case 0x6c: case 0x7d: case 0x7e: > /* Tiger Lake */ > case 0x8c: case 0x8d: > /* Tremont */ > -- > 2.7.4
