On Tue, Jan 10, 2006 at 03:52:36PM +0800, Tian, Kevin wrote:

> >* my implementation proposal
> >  - map xen's arch_domain::mm pte pages to dom0 virtual address space
> >    linearly with read-only protection.
> >    Since pte pages are managed by xen, I think it is reasonable for xen
> >    to handles tlb miss by dom0 on the phys2mach table area.
> >  - leave set_phys_to_machine() as nop.
> >
> >You seem to have different ideas.
> >Do you think that it is needed for dom0 to write phys2mach table directly?
> 
> No, I mostly agree with your approach on this issue with just one difference: 
> I would like to see phys2mach mapping ptes allocated within domain's 
> configured memory, instead of by Xen. Then you need to modify construct_dom0 
> and control panel to construct those ptes. Then Later Xen just constructs its 
> multi-level page tables with phys2mach table as L1 directly. By this way, 
> dom0 owns the memory and thus dom0 setups the mapping within its own range. I 
> always think dom0 has better knowledge about how allocated resource will be 
> final utilized and better to let dom0 to setup such stuff by its normal way 
> instead of Xen's supplement.
> 
> If we do this way, it's natural to let dom0 modify phys2mach table directly, 
> right?

By 'modify' do you mean that dom0 manages how to map 
phys2mach pages into the dom0 virtual address space, right?
If so, xen must verify tlb related operations by dom0 to inhibit
dom0 from writing to pte pages.

I think both proposals (yours and mine) may work well in functionality,
I'm not sure which performs better.

- Xen must verify dom0 tlb related operations to protect pte pages.
  i.e. some checks must be added to vcpu_itr_d(), ...
vs
- Xen tlb miss handler check whether fault address is in the phys2mach
  area and handles the fault specifically.
  i.e. The tlb miss handler of xen/ia64 must be modified to handle 
  tlb misses in the phys2mach area.

If I misunderstand, please correct.
-- 
yamahata

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