On Tue, Oct 09, 2007 at 04:23:20PM +0800, Xu, Anthony wrote: > > VHPT speculative load happens in the same time when tlb_miss handler is > executing. [...] > > Mf is to make sure that before modifying vhpt entry, vhpt entry must be > disabled, otherwise VHPT walker hardware may see enabled half modified vhpt > entry(definitely wrong entry), and load it into TLB cache.
I do understand why the VHPT entry must be disabled before being modified and enabled after. I do not understand why the MF is required. > > > Notice > For example, Write2 is after write1, > Write2 may be visible before write1. 'Visible' is defined only wrt other processor. But only the local processor will use the VHPT. Therefore, no need to make the write visible. In your example, if the memory is read between write1 and write2, the value will *always* be the value of write1. (if no other processor modifies the memory at the address). Tristan. _______________________________________________ Xen-ia64-devel mailing list Xen-ia64-devel@lists.xensource.com http://lists.xensource.com/xen-ia64-devel
