# HG changeset patch
# User Jimi Xenidis <[EMAIL PROTECTED]>
# Node ID 3e99cf85d57d5fa56fe5eb47b019f2989009d50c
# Parent  67953e195eb74f79ab2fd70315e585a7f8941161
[POWERPC][XEN] HID paranoia!

Used some HIDs to debug an issue, so decided to clean some stuff up.

Signed-off-by: Jimi Xenidis <[EMAIL PROTECTED]>
---
 xen/arch/powerpc/powerpc64/ppc970.c            |  109 ++++++++++++-------------
 xen/include/asm-powerpc/powerpc64/ppc970-hid.h |  105 ++++++++++++++++--------
 xen/include/asm-powerpc/powerpc64/processor.h  |    7 +
 3 files changed, 132 insertions(+), 89 deletions(-)

diff -r 67953e195eb7 -r 3e99cf85d57d xen/arch/powerpc/powerpc64/ppc970.c
--- a/xen/arch/powerpc/powerpc64/ppc970.c       Wed Aug 30 15:09:47 2006 -0400
+++ b/xen/arch/powerpc/powerpc64/ppc970.c       Wed Aug 30 18:01:15 2006 -0400
@@ -34,17 +34,17 @@
 
 struct rma_settings {
     int order;
-    int rmlr0;
-    int rmlr12;
+    int rmlr_0;
+    int rmlr_1_2;
 };
 
 static struct rma_settings rma_orders[] = {
-    { .order = 26, .rmlr0 = 0, .rmlr12 = 3, }, /*  64 MB */
-    { .order = 27, .rmlr0 = 1, .rmlr12 = 3, }, /* 128 MB */
-    { .order = 28, .rmlr0 = 1, .rmlr12 = 0, }, /* 256 MB */
-    { .order = 30, .rmlr0 = 0, .rmlr12 = 2, }, /*   1 GB */
-    { .order = 34, .rmlr0 = 0, .rmlr12 = 1, }, /*  16 GB */
-    { .order = 38, .rmlr0 = 0, .rmlr12 = 0, }, /* 256 GB */
+    { .order = 26, .rmlr_0 = 0, .rmlr_1_2 = 3, }, /*  64 MB */
+    { .order = 27, .rmlr_0 = 1, .rmlr_1_2 = 3, }, /* 128 MB */
+    { .order = 28, .rmlr_0 = 1, .rmlr_1_2 = 0, }, /* 256 MB */
+    { .order = 30, .rmlr_0 = 0, .rmlr_1_2 = 2, }, /*   1 GB */
+    { .order = 34, .rmlr_0 = 0, .rmlr_1_2 = 1, }, /*  16 GB */
+    { .order = 38, .rmlr_0 = 0, .rmlr_1_2 = 0, }, /* 256 GB */
 };
 
 static uint log_large_page_sizes[] = {
@@ -130,22 +130,21 @@ void cpu_initialize(int cpuid)
     mtdec(timebase_freq);
     mthdec(timebase_freq);
 
-    hid0.bits.nap = 1;
-    hid0.bits.dpm = 1;
-    hid0.bits.nhr = 1;
-    hid0.bits.hdice = 1; /* enable HDEC */
-    hid0.bits.eb_therm = 1;
-    hid0.bits.en_attn = 1;
+    hid0.bits.nap = 1;      /* NAP */
+    hid0.bits.dpm = 1;      /* Dynamic Power Management */
+    hid0.bits.nhr = 0;      /* ! Not Hard Reset */
+    hid0.bits.hdice_en = 1; /* enable HDEC */
+    hid0.bits.en_therm = 0; /* ! Enable ext thermal ints */
+    /* onlu debug Xen should do this */
+    hid0.bits.en_attn = 1; /* Enable attn instruction */
+
 #ifdef SERIALIZE
-    ulong s = 0;
-
-    s |= 1UL << (63-0);     /* one_ppc */
-    s |= 1UL << (63-2);     /* isync_sc */
-    s |= 1UL << (63-16);     /* inorder */
+    hid0.bits.one_ppc = 1;
+    hid0.bits.isync_sc = 1;
+    hid0.bits.inorder = 1;
     /* may not want these */
-    s |= 1UL << (63-1);     /* do_single */
-    s |= 1UL << (63-3);     /* ser-gp */
-    hid0.word |= s;
+    hid0.bits.do_single = 1;
+    hid0.bits.ser-gp = 1;
 #endif
 
     printk("CPU #%d: Hello World! SP = %lx TOC = %lx HID0 = %lx\n", 
@@ -153,36 +152,36 @@ void cpu_initialize(int cpuid)
 
     mthid0(hid0.word);
 
-    hid1.bits.bht_pm = 7;
-    hid1.bits.en_ls = 1;
-
-    hid1.bits.en_cc = 1;
-    hid1.bits.en_ic = 1;
-
-    hid1.bits.pf_mode = 2;
-
-    hid1.bits.en_if_cach = 1;
-    hid1.bits.en_ic_rec = 1;
-    hid1.bits.en_id_rec = 1;
-    hid1.bits.en_er_rec = 1;
-
-    hid1.bits.en_sp_itw = 1;
+    hid1.bits.bht_pm = 7; /* branch history table prediction mode */
+    hid1.bits.en_ls = 1; /* enable link stack */
+
+    hid1.bits.en_cc = 1; /* enable count cache */
+    hid1.bits.en_ic = 1; /* enable inst cache */
+
+    hid1.bits.pf_mode = 2; /* prefetch mode */
+
+    hid1.bits.en_if_cach = 1; /* i-fetch cacheability control */
+    hid1.bits.en_ic_rec = 1; /* i-cache parity error recovery */
+    hid1.bits.en_id_rec = 1; /* i-dir parity error recovery */
+    hid1.bits.en_er_rec = 1; /* i-ERAT parity error recovery */
+
+    hid1.bits.en_sp_itw = 1; /* En speculative tablewalks */
     mthid1(hid1.word);
 
     /* no changes to hid4 but we want to make sure that secondaries
      * are sane */
-    if (cpuid > 0)
-        mthid4(hid4.word);
-
-    hid5.bits.DCBZ_size = 0;
-    hid5.bits.DCBZ32_ill = 0;
+    hid4.bits.lg_pg_dis = 0;    /* make sure we enable large pages */
+    mthid4(hid4.word);
+
+    hid5.bits.DCBZ_size = 0; /* make dcbz size 32 bytes */
+    hid5.bits.DCBZ32_ill = 0; /* make dzbz 32byte illeagal */
     mthid5(hid5.word);
 
-#ifdef DUMP_HIDS
-    printk("hid0 0x%lx\n"
-           "hid1 0x%lx\n"
-           "hid4 0x%lx\n"
-           "hid5 0x%lx\n",
+#ifndef DUMP_HIDS
+    printk("hid0 0x%016lx\n"
+           "hid1 0x%016lx\n"
+           "hid4 0x%016lx\n"
+           "hid5 0x%016lx\n",
            mfhid0(), mfhid1(), mfhid4(), mfhid5());
 #endif
 
@@ -200,18 +199,18 @@ void cpu_init_vcpu(struct vcpu *v)
 
     hid4.word = mfhid4();
 
-    hid4.bits.lpes0 = 0; /* exceptions set MSR_HV=1 */
-    hid4.bits.lpes1 = 1; /* RMA applies */
-
-    hid4.bits.rmor = page_to_maddr(d->arch.rma_page) >> 26;
-
-    hid4.bits.lpid01 = d->domain_id & 3;
-    hid4.bits.lpid25 = (d->domain_id >> 2) & 0xf;
+    hid4.bits.lpes_0 = 0; /* external exceptions set MSR_HV=1 */
+    hid4.bits.lpes_1 = 1; /* RMA applies */
+
+    hid4.bits.rmor_0_15 = page_to_maddr(d->arch.rma_page) >> 26;
+
+    hid4.bits.lpid_0_1 = d->domain_id & 3;
+    hid4.bits.lpid_2_5 = (d->domain_id >> 2) & 0xf;
 
     rma_settings = cpu_find_rma(d->arch.rma_order + PAGE_SHIFT);
     ASSERT(rma_settings != NULL);
-    hid4.bits.rmlr0 = rma_settings->rmlr0;
-    hid4.bits.rmlr12 = rma_settings->rmlr12;
+    hid4.bits.rmlr_0 = rma_settings->rmlr_0;
+    hid4.bits.rmlr_1_2 = rma_settings->rmlr_1_2;
 
     v->arch.cpu.hid4.word = hid4.word;
 }
diff -r 67953e195eb7 -r 3e99cf85d57d 
xen/include/asm-powerpc/powerpc64/ppc970-hid.h
--- a/xen/include/asm-powerpc/powerpc64/ppc970-hid.h    Wed Aug 30 15:09:47 
2006 -0400
+++ b/xen/include/asm-powerpc/powerpc64/ppc970-hid.h    Wed Aug 30 18:01:15 
2006 -0400
@@ -29,22 +29,30 @@
 
 union hid0 {
     struct hid0_bits {
-        ulong   _unused_0_8:    9;
-        ulong   nap:            1;
-        ulong   _unused_10:     1;
-        ulong   dpm:            1;  /* Dynamic Power Management */
-        ulong   _unused_12_14:  3;
-        ulong   nhr:            1;  /* Not Hard Reset */
-        ulong   inorder:        1;
+        ulong   one_ppc:        1; /* One PowerPC AS insn per dispatch group */
+        ulong   do_single:      1; /* Single group completion */
+        ulong   isync_sc:       1; /* Disable isync scoreboard optimization */
+        ulong   ser_gp:         1; /* Serial Group Dispatch */
+        ulong  _reserved_04_08: 5;
+        ulong   nap:            1; /* Nap */
+        ulong   _reserved_10:   1;
+        ulong   dpm:            1; /* Dynamic Power Management */
+        ulong   _reserved_12:   1;
+        ulong   tg:             1; /* Perfmon threshold granualrity control */
+        ulong   hang_dis:       1; /* Disable cpu hang detection mechanism */
+        ulong   nhr:            1; /* Not Hard Reset */
+        ulong   inorder:        1; /* Serial Group Issue */
         ulong   _reserved17:    1;
-        ulong   tb_ctrl:        1;
-        ulong   ext_tb_enb:     1;  /* timebase is linked to external clock */
-        ulong   _unused_20_22:  3;
-        ulong   hdice:          1;  /* HDEC enable */
-        ulong   eb_therm:       1;  /* Enable ext thermal ints */
+        ulong   tb_ctrl:        1; /* Enable time base couting while stopped */
+        ulong   ext_tb_enb:     1; /* timebase is linked to external clock */
+        ulong   _unused_20_21:  2;
+        ulong   ciabr_en:       1;  /* CIABR enable */
+        ulong   hdice_en:       1;  /* HDEC enable */
+        ulong   en_therm:       1;  /* Enable ext thermal ints */
         ulong   _unused_25_30:  6;
         ulong   en_attn:        1;  /* Enable attn instruction */
-        ulong   _unused_32_63:  32;
+        ulong   en_mck:         1;  /* En external machine check interrupts */
+        ulong   _unused_33_63:  31;
     } bits;
     ulong word;
 };
@@ -62,11 +70,11 @@ union hid1 {
         ulong en_ic_rec:        1; /* i-cache parity error recovery */
         ulong en_id_rec:        1; /* i-dir parity error recovery */
         ulong en_er_rec:        1; /* i-ERAT parity error recovery */
-        ulong ic_pe:            1;
-        ulong icd0_pe:          1;
+        ulong ic_pe:            1; /* Force instruction cache parity error */
+        ulong icd0_pe:          1; /* Force insn cache dir 0 parity error */
         ulong _reserved_16:     1;
-        ulong ier_pe:           1;
-        ulong en_sp_itw:        1;
+        ulong ier_pe:           1; /* force i-ERAT parity error (inject) */
+        ulong en_sp_itw:        1; /* En speculative tablewalks */
         ulong _reserved_19_63:  45;
     } bits;
     ulong word;
@@ -74,32 +82,61 @@ union hid1 {
 
 union hid4 {
     struct hid4_bits {
-        ulong   lpes0:          1;  /* LPAR Environment Selector bit 0 */
-        ulong   rmlr12:         2;  /* RMLR 1:2 */
-        ulong   lpid25:         4;  /* LPAR ID bits 2:5 */
-        ulong   rmor:           16; /* real mode offset region */
-        ulong   rm_ci:          1;  /* real mode cache-inhibit */
-        ulong   force_ai:       1;  /* Force alignment interrupt */
-        ulong   _unused:        32;
-        ulong   lpes1:          1;  /* LPAR Environment Selector bit 1 */
-        ulong   rmlr0:          1;  /* RMLR 0 */
+        ulong   lpes_0:         1; /* LPAR Environment Selector bit 0 */
+        ulong   rmlr_1_2:       2; /* RMLR 1:2 */
+        ulong   lpid_2_5:       4; /* LPAR ID bits 2:5 */
+        ulong   rmor_0_15:     16; /* real mode offset region */
+        ulong   rm_ci:          1; /* real mode cache-inhibit */
+        ulong   force_ai:       1; /* Force alignment interrupt */
+        ulong   dis_pref:       1; /* disable prefetching */
+        ulong   res_pref:       1; /* reset data prefetching mechanism */
+        ulong   en_sp_dtw:      1; /* enable speculative load tablewalk */
+        ulong   l1dc_flsh:      1; /* L1 cache flash invalidate */
+        ulong   dis_derpc:      2; /* Disable d-ERAT parity checking */
+        ulong   dis_derpg:      1; /* Disable d-ERAT parity generation */
+        ulong   dis_derat:      2; /* Disable d-ERAT */
+        ulong   dis_dctpc:      2; /* Dis data cache tag paritiy checking */
+        ulong   dis_dctpg:      1; /* Dis data cache tag paritiy generation */
+        ulong   dis_dcset:      2; /* Disable data cache set */
+        ulong   dis_dcpc:       2; /* Disable data cache paritiy checking */
+        ulong   dis_dcpg:       1; /* Disable data cache paritiy generation */
+        ulong   dis_dcrtpc:     2; /* Disable data cache real add tag parity */
+        ulong   dis_tlbpc:      4; /* Disable TLB paritiy checking */
+        ulong   dis_tlbpg:      1; /* Disable TLB paritiy generation */
+        ulong   dis_tlbset:     4; /* Disable TLB set */
+        ulong   dis_slbpc:      1; /* Disable SLB paritiy checking */
+        ulong   dis_slbpg:      1; /* Disable SLB paritiy generation */
+        ulong   mck_inj:        1; /* Machine check inject enable */
+        ulong   dis_stfwd:      1; /* Disbale store forwarding */
+        ulong   lpes_1:         1;  /* LPAR Environment Selector bit 1 */
+        ulong   rmlr_0:         1;  /* RMLR 0 */
         ulong   _reserved:      1;
         ulong   dis_splarx:     1;  /* Disable spec. lwarx/ldarx */
         ulong   lg_pg_dis:      1;  /* Disable large page support */
-        ulong   lpid01:         2;  /* LPAR ID bits 0:1 */
+        ulong   lpid_0_1:       2;  /* LPAR ID bits 0:1 */
     } bits;
     ulong word;
 };
 
 union hid5 {
     struct hid5_bits {
-        ulong  _reserved_0_31:  32;
-        ulong   hrmor:          16;
-        ulong   _reserver_48_49:2;
-        ulong   _unused_50_55:  6;
-        ulong   DCBZ_size:      1;
-        ulong   DCBZ32_ill:     1;
-        ulong  _unused_58_63:   6;
+        ulong _reserved_0_31: 32;
+        ulong hrmor_0_15:     16;
+        ulong _reserved_48_49: 2;
+        ulong DC_mck:          1; /* Machine check enabled for dcache errors */
+        ulong dis_pwrsave:     1; /* Dis pwrsave on on L1 and d-ERAT */
+        ulong force_G:         1; /* Force gaurded load */
+        ulong DC_repl:         1; /* D-Cache replacement algo */
+        ulong hwr_stms:        1; /* Number of available HW prefetch streams */
+        ulong dst_noop:        1; /* D-stream Touch no-op */
+        ulong DCBZ_size:       1; /* make dcbz size 32 bytes */
+        ulong DCBZ32_ill:      1; /* make dzbz 32byte illeagal */
+        ulong tlb_map:         1; /* TLB mapping */
+        ulong lmq_port:        1; /* Demand miss (LMQ to STS) */
+        ulong lmq_size_0:      1; /* number of outstanding req. to STS */
+        ulong  _reserved_61:   1;
+        ulong  tch_nop:        1; /* make dcbtand dcbtst ack like no-ops */
+        ulong  lmq_size_1:     1; /* second bit to lmq_size_0 */
     } bits;
     ulong word;
 };
diff -r 67953e195eb7 -r 3e99cf85d57d 
xen/include/asm-powerpc/powerpc64/processor.h
--- a/xen/include/asm-powerpc/powerpc64/processor.h     Wed Aug 30 15:09:47 
2006 -0400
+++ b/xen/include/asm-powerpc/powerpc64/processor.h     Wed Aug 30 18:01:15 
2006 -0400
@@ -138,6 +138,12 @@ static inline void mthid0(ulong val)
     __asm__ __volatile__ (
             "sync\n"
             "mtspr %0, %1\n"
+            "mfspr %0, %1\n"
+            "mfspr %0, %1\n"
+            "mfspr %0, %1\n"
+            "mfspr %0, %1\n"
+            "mfspr %0, %1\n"
+            "mfspr %0, %1\n"
             "isync\n"
             : : "i"(SPRN_HID0), "r"(val));
 }
@@ -152,6 +158,7 @@ static inline void mthid1(ulong val)
 {
     __asm__ __volatile__ (
             "sync\n"
+            "mtspr %0, %1\n"
             "mtspr %0, %1\n"
             "isync\n"
             : : "i"(SPRN_HID1), "r"(val));

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