The code of concern seems well suited to catch a spurious interrupt
storm, since when a valid external interrupt is recieved, the counter is
reset.  But given that we don't take our first external until way into
dom0's boot, we are actually asserting that 100 spurious interrupts
won't be received over a fairly long period of time.

I can't find any documents regarding expected spurious interrupt rates. Can anyone with knowledge in this area comment about the code of concern?

All edge-triggered interrupts can cause spurious interrupts; this
is normal.  For example, a second edge interrupt (on the same line)
can come in before the first has been handled.  The rate at which
this happens should be really low.

The CPC9x5 interrupt controller has an issue though that manifests
itself as lots of spurious interrupts all over the place.  Those
are interspersed with valid interrupts, there is no functional
problem; it can turn into a performance problem though.


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