On Dec 2, 2006, at 10:18 AM, Jimi Xenidis wrote:


On Dec 2, 2006, at 2:37 AM, Segher Boessenkool wrote:

My question remains: did you try with NAP disabled and
DPM enabled?

I see, so:
  HID0[NAP]=1
  HID0[DPM]=1
  MSR[POW]=1

is NAP and is different than:
  HID0[NAP]=0
  HID0[DPM]=1
  MSR[POW]=1
which is something else?

Sure I'll try that.

The following patch results in SMP stability on Maple. Amos, Kawachiya-san, could one of you ack it with the JS20 in question?

diff -r 0e85b389980a xen/arch/powerpc/powerpc64/ppc970.c
--- a/xen/arch/powerpc/powerpc64/ppc970.c       Fri Dec 01 19:11:02 2006 -0500
+++ b/xen/arch/powerpc/powerpc64/ppc970.c       Sat Dec 02 10:26:50 2006 -0500
@@ -193,10 +193,10 @@ void cpu_initialize(int cpuid)
     mtdec(timebase_freq);
     mthdec(timebase_freq);
- /* FIXME Do not set the NAP and DPM bits in HID0 until we have had a
-     * chance to audit the safe halt and idle loop code. */
+    /* FIXME Do not set the NAP bit in HID0 until we have had a chance
+     * to audit the safe halt and idle loop code. */
     hid0.bits.nap = 0;      /* NAP */
-    hid0.bits.dpm = 0;      /* Dynamic Power Management */
+    hid0.bits.dpm = 1;      /* Dynamic Power Management */
     hid0.bits.nhr = 1;      /* Not Hard Reset */
     hid0.bits.hdice_en = 1; /* enable HDEC */





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