On Mar 20, 2007, at 11:36 AM, Hollis Blanchard wrote:

On Mon, 2007-03-19 at 15:30 +0100, Christian Ehrhardt wrote:
I have one more questions regarding the oprofile extension to work in
xenppc guests.

The plain linux implementation sets !always! the vector for the
performance interrupt 0xf00 to the function
"performance_monitor_exception" in head32.S/head64.S. Depending on
wether linux starts profiling this function is set to a dummy or the
"real" handler of e.g. oprofile.
Now in the virtualized environment each guest set's its own interrupt
handler for 0xf00 (Performance monitor interrupt).

Yes, each guest decided to set it to a dummy or a real handler.

Because we are
running with LPSE[1]=0 as Jimi wrote before the performance interrupt
while a Dom is running should be handled from the domain because nothing
sets MSR[HV] to 1.

OK, so performance monitor interrupts go directly to the guest.

My question is now if the address translation & virtualization ensures that each perf interrupt will be a) served by the right function adress
and b) in the domain. Maybe there is some exclusive part involved and
the different writes of the 0xf00 vector may overwrite each other or
something similar - that's why I want to ask to be sure.

On this architecure, all interrupts turn "translate off", MSR[IR|DR] =0b00. The hypervisor design provided by using LPES[0]=1 allows us to create an area that the domain can consider "translate off" we call this the Real Mode Area (RMA) and each RMA must be unique to every guest. So each guest is free to install its own unique interrupt handlers, since any interrupts that do not modify MSR[HV] will cause the the CPU to execute at the same effective address offset into the RMA.

Example of a system with two DomU guests that enabled the performance
0xf00 -> undef?

I'm not sure what to do about a perfmon interrupt in Xen. Since we're
saving/restoring the perfmon register state on domain entry/exit, can we
just disable those interrupts while running Xen?

Yes with MMCR0[HFC]

0xf00 -> default_pmc_irq
0xf00 ->    pmc_irq_handler1
0xf00 ->    pmc_irq_handler2

I don't understand the question about translation. The domains do not
share code. For example, it is not possible for an interrupt in Dom1 to
trigger an exception handler in Dom0.

I think the Christian believes all domains share the same interrupt vectors, I hope the RMA discussion has clarified that.

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