[XEN][POWERPC][PATCH 3/3] Guest Perfmon implementation - disable pmu in xen space, spr access functions, spr encodings
->attachment

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Grüsse / regards, Christian Ehrhardt

IBM Linux Technology Center, Open Virtualization
+49 7031/16-3385
[EMAIL PROTECTED]
[EMAIL PROTECTED]

IBM Deutschland Entwicklung GmbH
Vorsitzender des Aufsichtsrats: Johann Weihen Geschäftsführung: Herbert Kircher Sitz der Gesellschaft: Böblingen
Registergericht: Amtsgericht Stuttgart, HRB 243294

# HG changeset patch
# User Christian Ehrhardt <[EMAIL PROTECTED]>
# Date 1178509486 -7200
# Node ID be31124bbec216693cb5758ee2e6d87b3fd292b2
# Parent  16a5031473951e5a69680db92924e3fc327e8f67
[XEN][POWERPC][PATCH 3/3] Guest Perfmon implementation - disable pmu in xen space, spr access functions, spr encodings
This is the first step of enabling oprofile performance monitoring on the xenppc platform. It allows users to work with oprofile in Dom0 and DomU guests as known from non virtualized ppc-linux.
This patch:
- ensuring MMCR0[FCH]=1 (disable profiling hardware in xen space)
- registers the performance monitor exception handler
- implement new helper functions to access special purpose registers
- defines needed special purpose register encodings

Signed-off-by: Christian Ehrhardt <[EMAIL PROTECTED]>

diff -r 16a503147395 -r be31124bbec2 xen/arch/powerpc/of_handler/papr.S
--- a/xen/arch/powerpc/of_handler/papr.S	Mon May 07 05:38:31 2007 +0200
+++ b/xen/arch/powerpc/of_handler/papr.S	Mon May 07 05:44:46 2007 +0200
@@ -67,7 +67,7 @@ PAPR(5, 1,papr_pci_config_read, H_PCI_CO
 PAPR(5, 1,papr_pci_config_read, H_PCI_CONFIG_READ)
 PAPR(5, 0,papr_pci_config_write, H_PCI_CONFIG_WRITE)
 
-	PAPR(5, 1,papr_grant_logical, H_GRANT_LOGICAL)
+PAPR(5, 1,papr_grant_logical, H_GRANT_LOGICAL)
 PAPR(1, 1,papr_accept_logical, H_ACCEPT_LOGICAL)
 PAPR(0, 2,papr_rescind_logical, H_RESCIND_LOGICAL)
 PAPR(3, 0,papr_register_vterm, H_REGISTER_VTERM)
diff -r 16a503147395 -r be31124bbec2 xen/arch/powerpc/powerpc64/exceptions.S
--- a/xen/arch/powerpc/powerpc64/exceptions.S	Mon May 07 05:38:31 2007 +0200
+++ b/xen/arch/powerpc/powerpc64/exceptions.S	Mon May 07 05:44:46 2007 +0200
@@ -105,6 +105,12 @@ 1:
     nop
 .endm
 
+.macro PMU_SAVE_STATE scratch
+    mfspr \scratch,SPRN_MMCR0             /* ensure MMCR0[FCH] is 1 */
+    ori \scratch,\scratch,MMCR0_FCH
+    mtspr SPRN_MMCR0, \scratch
+.endm
+
 .macro EXCEPTION_HEAD parea continue
     /* make room for cpu_user_regs */
     subi r1, r1, STACK_VOLATILE_AREA + UREGS_sizeof
@@ -156,7 +162,7 @@ 1:
     ori r0, r0, [EMAIL PROTECTED]
     mtmsrd r0
 
-
+    PMU_SAVE_STATE r0
 .endm
 
 /* For exceptions that use HSRR0/1 (preserving the OS's SRR0/1). */
@@ -183,6 +189,7 @@ 1:
     ori r0, r0, [EMAIL PROTECTED]
     mtmsrd r0
 
+    PMU_SAVE_STATE r0
 .endm
 
 /* Hypervisor exception handling code; copied to physical address zero. */
@@ -328,6 +335,13 @@ ex_fp:
     li r0, 0xe00 /* exception vector for GDB stub */
     bctr
 
+    . = 0xf00
+ex_perfmon:
+    GET_STACK r13 SPRN_SRR1
+    EXCEPTION_HEAD r13 ex_perfmon_continued
+    li r0, 0xf00 /* exception vector for GDB stub */
+    bctr
+
     .align 3
     .globl exception_vectors_end
 
@@ -445,6 +459,16 @@ ex_dec_continued:
 ex_dec_continued:
     EXCEPTION_SAVE_STATE r1
     LOADADDR r12, do_dec
+    mr r3, r1                           /* pass pointer to cpu_user_regs */
+    subi r1, r1, STACK_FRAME_OVERHEAD   /* make a "caller" stack frame */
+    CALL_CFUNC r12
+
+    addi r1, r1, STACK_FRAME_OVERHEAD   /* restore stack to cpu_user_regs */
+    b fast_resume
+
+ex_perfmon_continued:
+    EXCEPTION_SAVE_STATE r1
+    LOADADDR r12, do_perfmon
     mr r3, r1                           /* pass pointer to cpu_user_regs */
     subi r1, r1, STACK_FRAME_OVERHEAD   /* make a "caller" stack frame */
     CALL_CFUNC r12
diff -r 16a503147395 -r be31124bbec2 xen/include/asm-powerpc/processor.h
--- a/xen/include/asm-powerpc/processor.h	Mon May 07 05:38:31 2007 +0200
+++ b/xen/include/asm-powerpc/processor.h	Mon May 07 05:44:46 2007 +0200
@@ -200,6 +200,143 @@ static inline ulong mfr1(void)
     return r1;
 }
 
+/*
+static inline void mtspr(ulong rn, ulong val)
+{
+    asm volatile ("mtspr %0, %1" : : "i"(rn), "r"(val));
+}
+static inline ulong mfspr(ulong rn)
+{
+    ulong rval;
+    asm volatile ("mfspr %0, %1" : "=r"(rval) : "i"(rn));
+    return rval;
+}
+*/
+static inline void mtmmcr0(ulong val)
+{
+    asm volatile ("mtspr %0, %1" : : "i"(SPRN_MMCR0), "r"(val));
+}
+static inline ulong mfmmcr0(void)
+{
+    ulong rval;
+    asm volatile ("mfspr %0, %1" : "=r"(rval) : "i"(SPRN_MMCR0));
+    return rval;
+}
+static inline void mtmmcr1(ulong val)
+{
+    asm volatile ("mtspr %0, %1" : : "i"(SPRN_MMCR1), "r"(val));
+}
+static inline ulong mfmmcr1(void)
+{
+    ulong rval;
+    asm volatile ("mfspr %0, %1" : "=r"(rval) : "i"(SPRN_MMCR1));
+    return rval;
+}
+static inline void mtmmcra(ulong val)
+{
+    asm volatile ("mtspr %0, %1" : : "i"(SPRN_MMCRA), "r"(val));
+}
+static inline ulong mfmmcra(void)
+{
+    ulong rval;
+    asm volatile ("mfspr %0, %1" : "=r"(rval) : "i"(SPRN_MMCRA));
+    return rval;
+}
+static inline void mtpmc1(ulong val)
+{
+    asm volatile ("mtspr %0, %1" : : "i"(SPRN_PMC1), "r"(val));
+}
+static inline ulong mfpmc1(void)
+{
+    ulong rval;
+    asm volatile ("mfspr %0, %1" : "=r"(rval) : "i"(SPRN_PMC1));
+    return rval;
+}
+static inline void mtpmc2(ulong val)
+{
+    asm volatile ("mtspr %0, %1" : : "i"(SPRN_PMC2), "r"(val));
+}
+static inline ulong mfpmc2(void)
+{
+    ulong rval;
+    asm volatile ("mfspr %0, %1" : "=r"(rval) : "i"(SPRN_PMC2));
+    return rval;
+}
+static inline void mtpmc3(ulong val)
+{
+    asm volatile ("mtspr %0, %1" : : "i"(SPRN_PMC3), "r"(val));
+}
+static inline ulong mfpmc3(void)
+{
+    ulong rval;
+    asm volatile ("mfspr %0, %1" : "=r"(rval) : "i"(SPRN_PMC3));
+    return rval;
+}
+static inline void mtpmc4(ulong val)
+{
+    asm volatile ("mtspr %0, %1" : : "i"(SPRN_PMC4), "r"(val));
+}
+static inline ulong mfpmc4(void)
+{
+    ulong rval;
+    asm volatile ("mfspr %0, %1" : "=r"(rval) : "i"(SPRN_PMC4));
+    return rval;
+}
+static inline void mtpmc5(ulong val)
+{
+    asm volatile ("mtspr %0, %1" : : "i"(SPRN_PMC5), "r"(val));
+}
+static inline ulong mfpmc5(void)
+{
+    ulong rval;
+    asm volatile ("mfspr %0, %1" : "=r"(rval) : "i"(SPRN_PMC5));
+    return rval;
+}
+static inline void mtpmc6(ulong val)
+{
+    asm volatile ("mtspr %0, %1" : : "i"(SPRN_PMC6), "r"(val));
+}
+static inline ulong mfpmc6(void)
+{
+    ulong rval;
+    asm volatile ("mfspr %0, %1" : "=r"(rval) : "i"(SPRN_PMC6));
+    return rval;
+}
+#ifdef CONFIG_PPC64
+static inline void mtpmc7(ulong val)
+{
+    asm volatile ("mtspr %0, %1" : : "i"(SPRN_PMC7), "r"(val));
+}
+static inline ulong mfpmc7(void)
+{
+    ulong rval;
+    asm volatile ("mfspr %0, %1" : "=r"(rval) : "i"(SPRN_PMC7));
+    return rval;
+}
+static inline void mtpmc8(ulong val)
+{
+    asm volatile ("mtspr %0, %1" : : "i"(SPRN_PMC8), "r"(val));
+}
+static inline ulong mfpmc8(void)
+{
+    ulong rval;
+    asm volatile ("mfspr %0, %1" : "=r"(rval) : "i"(SPRN_PMC8));
+    return rval;
+}
+#endif
+static inline ulong mfsdar(void)
+{
+    ulong rval;
+    asm volatile ("mfspr %0, %1" : "=r"(rval) : "i"(SPRN_SDAR));
+    return rval;
+}
+static inline ulong mfsiar(void)
+{
+    ulong rval;
+    asm volatile ("mfspr %0, %1" : "=r"(rval) : "i"(SPRN_SIAR));
+    return rval;
+}
+
 static inline void mtsprg0(ulong val)
 {
     __asm__ __volatile__ ("mtspr %0, %1" : : "i"(SPRN_SPRG0), "r"(val));
diff -r 16a503147395 -r be31124bbec2 xen/include/asm-powerpc/reg_defs.h
--- a/xen/include/asm-powerpc/reg_defs.h	Mon May 07 05:38:31 2007 +0200
+++ b/xen/include/asm-powerpc/reg_defs.h	Mon May 07 05:44:46 2007 +0200
@@ -166,8 +166,36 @@
 #define SPRN_LPCR   318
 #define SPRN_LPIDR  319
 
+/* Performance monitor spr encodings */
+#define SPRN_MMCRA  786
+#define   MMCRA_SAMPHV    UL(0x10000000) /* state of MSR HV when SIAR set */
+#define   MMCRA_SAMPPR    UL(0x08000000) /* state of MSR PR when SIAR set */
+#define   MMCRA_SAMPLE_ENABLE UL(0x00000001) /* enable sampling */
+#define SPRN_PMC1   787
+#define SPRN_PMC2   788
+#define SPRN_PMC3   789
+#define SPRN_PMC4   790
+#define SPRN_PMC5   791
+#define SPRN_PMC6   792
+#ifdef CONFIG_PPC64
+#define NUM_PMCS 8
+#define SPRN_PMC7   793
+#define SPRN_PMC8   794
+#else
+#define NUM_PMCS 6
+#endif
+#define SPRN_MMCR0  795
+#define   MMCR0_FC      UL(0x80000000) /* freeze counters */
+#define   MMCR0_FCS     UL(0x40000000) /* freeze in supervisor state */
+#define   MMCR0_FCP     UL(0x20000000) /* freeze in problem state */
+#define   MMCR0_FCM1    UL(0x10000000) /* freeze counters while MSR mark = 1 */
+#define   MMCR0_FCM0    UL(0x08000000) /* freeze counters while MSR mark = 0 */
+#define   MMCR0_PMAE    UL(0x04000000) /* performance monitor alert enabled */
+#define   MMCR0_PMAO    UL(0x00000080) /* performance monitor alert occurred */
+#define   MMCR0_FCH     UL(0x00000001) /* freeze conditions in hypervisor */
 #define SPRN_SIAR   796
 #define SPRN_SDAR   797
+#define SPRN_MMCR1  798
 
 /* As defined for PU G4 */
 #define SPRN_HID0   1008
diff -r 16a503147395 -r be31124bbec2 xen/include/asm-powerpc/xenoprof.h
--- a/xen/include/asm-powerpc/xenoprof.h	Mon May 07 05:38:31 2007 +0200
+++ b/xen/include/asm-powerpc/xenoprof.h	Mon May 07 05:44:46 2007 +0200
@@ -21,6 +21,87 @@
 #ifndef __ASM_PPC_XENOPROF_H__
 #define __ASM_PPC_XENOPROF_H__
 
-/* unimplemented */
+#include <xen/config.h>
+#include <xen/types.h>
+#include <xen/sched.h>
+#include <public/xen.h>
+
+/* All the classic PPC parts use these */
+static inline unsigned int ctr_read(unsigned int i)
+{
+	switch(i) {
+	case 0:
+		return mfpmc1();
+	case 1:
+		return mfpmc2();
+	case 2:
+		return mfpmc3();
+	case 3:
+		return mfpmc4();
+	case 4:
+		return mfpmc5();
+	case 5:
+		return mfpmc6();
+
+/* No PPC32 chip has more than 6 so far */
+#ifdef CONFIG_PPC64
+	case 6:
+		return mfpmc7();
+	case 7:
+		return mfpmc8();
+#endif
+	default:
+		return 0;
+	}
+}
+
+static inline void ctr_write(unsigned int i, unsigned int val)
+{
+	switch(i) {
+	case 0:
+		mtpmc1(val);
+		break;
+	case 1:
+		mtpmc2(val);
+		break;
+	case 2:
+		mtpmc3(val);
+		break;
+	case 3:
+		mtpmc4(val);
+		break;
+	case 4:
+		mtpmc5(val);
+		break;
+	case 5:
+		mtpmc6(val);
+		break;
+/* No PPC32 chip has more than 6, yet */
+#ifdef CONFIG_PPC64
+    case 6:
+        mtpmc7(val);
+        break;
+    case 7:
+        mtpmc8(val);
+        break;
+#endif
+    default:
+        break;
+    }
+}
+
+static inline void print_perf_status()
+{
+    ulong mmcr0 = mfmmcr0();
+    ulong mmcr1 = mfmmcr1();
+    ulong mmcra = mfmmcra();
+    ulong sdar = mfsdar();
+    ulong siar = mfsiar();
+    printk("MMCR0 0x%0lX\n",mmcr0);
+    printk("MMCR1 0x%0lX\n",mmcr1);
+    printk("MMCRA 0x%0lX\n",mmcra);
+    printk("SIAR 0x%0lX\n",siar);
+    printk("SDAR 0x%0lX\n",sdar);
+}
 
 #endif
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