Heikki Lindholm wrote: > Gilles Chanteperdrix kirjoitti: > > Heikki Lindholm wrote: > > > Yes, Altivec is separate from the FPU. Hopefully nobody uses FPU in the > > > kernel - AFAIK currently not, but you never know about closed-source > > > drivers and such. Whereas, Altivec, I think, is something that should, > > > eventually, be supported by the real-time domain, too. Adding Altivec > > > support is very similar to the existing fpu support, and being that it > > > has to tackle the kernel-using-altivec issue anyway, it's probably > > nicer > > > to add fpu kernel support as well. Only problem is that it will > > increase > > > the context switch time. > > > > Maybe we could add an XNSIMD flag for Altivec and SSE, distinct from > > XNFPU, so that only the task that really use SIMD instructions would pay > > the price of the switch ? > > Sounds like a plan to me.
Actually that is a bad idea on x86, because the fxsave instruction that saves the whole FP context, including SSE registers, is faster than the fsave instruction that only save the regular FP registers. We are discussing about operations that take around 500 ns on a 1GHz PIII with cold cache. I would be curious to know how many cycles the FP and altivec registers save take on power pc. -- Gilles Chanteperdrix. _______________________________________________ Xenomai-core mailing list Xenomaifirstname.lastname@example.org https://mail.gna.org/listinfo/xenomai-core