reading through timer code of Xenomai I just wondered (again) what our
official model of TSCs on multiprocessor boxes are:

1) (practically) perfectly synchronised without offset

2) synchronised but with (unknown?) offset

3) unsynchronised

I'm asking because I worried about timestamps taken on external events
like interrupts on one CPU and are then used to trigger some timed
operation on another. Such things may easily happen via RTDM devices
where we do not communicate the CPU source of event timestamps. But
there is also other code influenced by the TSC model, e.g. data
collection and evaluation for CPU load stats.


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