Sebastian Smolorz wrote:
> Gilles Chanteperdrix wrote:
>>You can avoid this problem by adding LATCH or
>>__ipipe_mach_ticks_per_jiffy to the current value of the match register
>>in the timer interrupt, as it is done for the SA and PXA architectures.
> Unfortunately, this solution is not applicable. The timers of PXA and SA are
> counting up whereas the S3C24xx timers are counting down to zero. There is no
> match register for the next interrupt. In contrast, the timer must be
> programmed with the new dec value directly, thus stopping it for the time of
Right, you are in the same case as the integrator platform.
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