Gilles Chanteperdrix wrote:
> BOUIN Alexandre wrote:
> > We (Adeneo) are working on a ARM AT91 RTAI. We encountered some
> difficulties such tsc one : in periodic mode, we reload our timer
> automatically in order to avoid reprogramming it. TC timer increments a 16
> byte register, which is not enough for a tsc (64 bytes). tsc need to be
> emulated on ARM.
> > With oneshot mode, tsc is updating the 4 least significant
> bytes and then increments other bytes each time counter go back to zero
> > With our periodic mode, timer reloads himself so we need to
> change tsc emulation by incrementing tsc like this : tsc += period.
> > We made some evolutions on ipipe which will be applied to a hal
> I intend to rework I-pipe tsc emulation for arms with a free-running
> counter. In order to reduce the tsc read operations:
> - it should use the (uninterruptible) ldm instruction to load the 64
> bits counter without masking interrupts;
> - the 64 bits counter should not be updated at each read, but only from
> time to time, the best place to do this is Linux timer interrupt.
I never did the calculation before, but the TC free-running counter
wraps every 40 milliseconds, so Linux timer interrupt is not often
enough to update the 64 bits counter. The only safe place to update the
64 bits counter seems to be __ipipe_mach_acktimer.
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