Gregory CLEMENT wrote:
 > 2007/6/8, Gilles Chanteperdrix <[EMAIL PROTECTED]>:
 > > BOUIN Alexandre wrote:
 > >  >              We (Adeneo) are working on a ARM AT91 RTAI. We encountered 
 > > some difficulties such tsc one : in periodic mode, we reload our timer 
 > > automatically in order to avoid reprogramming it. TC timer increments a 16 
 > > byte register, which is not enough for a tsc (64 bytes). tsc need to be 
 > > emulated on ARM.
 > >  >              With oneshot mode, tsc is updating the 4 least significant 
 > > bytes and then increments other bytes each time counter go back to zero 
 > > value.
 > >  >
 > >  >              With our periodic mode, timer reloads himself so we need 
 > > to change tsc emulation by incrementing tsc like this : tsc += period.
 > >  >              We made some evolutions on ipipe which will be applied to 
 > > a hal patch.
 > >
 > > I intend to rework I-pipe tsc emulation for arms with a free-running
 > > counter. In order to reduce the tsc read operations:
 > > - it should use the (uninterruptible) ldm instruction to load the 64
 > >   bits counter without masking interrupts;
 > > - the 64 bits counter should not be updated at each read, but only from
 > >   time to time, the best place to do this is Linux timer interrupt.
 > 
 > If 64 bits counter is not updated at each read, we still need to load
 > it, read the current value of free-running counter, compare it to its
 > last value when 64 bits counter was updated. If we don't do this we
 > loose granularity.
 > So the gain is only on not writing the 64  bits counter, or maybe I
 > missed something ?

We can use the ldm instruction which is not interruptible and thus
remove interrupt masking as well.

-- 


                                            Gilles Chanteperdrix.

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