Thanks for the reply. The timer register has the following layout: bit
0-15: reload, bit 16-31: counter. Thats why I put 0xFFFF0000. Looking
at the code this cannot work so I added an extra field to indicate the
shift after applying the mask.

Now the userspace latency test prorgam gives valid latencies, sadly
it's still -1ms to 3ms latency.

How should I proceed troubleshooting this?
Looking at the ipipe trace it looks the task is brought op quite fast
after the interrupt fires so I think it is set at the wrong time, I'm
going to look into this.

Bertold Van den Bergh
On Sun, Sep 18, 2011 at 3:09 PM, Gilles Chanteperdrix
<gilles.chanteperd...@xenomai.org> wrote:
> On 09/17/2011 05:15 PM, Bertold Van den Bergh wrote:
>> Hello,
>> I am trying to port Xenomai to the freescale stmp3xxx cpu (I.MX233).
>> I added TSC code from plat-s3c24xx as this processor also uses a 16
>> bit downcounter based timer. I run the system tick counter and the TSC
>> freerunning counter at 32KHz (I plan to speed it up to increase
>> precision but I have a question about that). I have monitored the TSC
>> output and it is a monotonic count without jumps forward or backward.
>> Xenomai and linux boots fine. I can also start xenomai tasks, and they
>> even appear to work to some extent.
> The mask member filled by __ipipe_mach_get_tscinfo is wrong, the right
> mask for a 16 bits counter is 0x0000ffff
> --
>                                                                Gilles.

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