On 09/18/2011 04:43 PM, Bertold Van den Bergh wrote: > Hello, > > Thanks for the reply. The timer register has the following layout: bit > 0-15: reload, bit 16-31: counter. Thats why I put 0xFFFF0000. Looking > at the code this cannot work so I added an extra field to indicate the > shift after applying the mask.
You should really upgrade your I-pipe tree to a more recent one, where the support for tsc emulation was factored. You would add the new case to the tsc implementations in kernel-space, and nowhere else. When you are done, please send a patch. > > Now the userspace latency test prorgam gives valid latencies, sadly > it's still -1ms to 3ms latency. > > How should I proceed troubleshooting this? > Looking at the ipipe trace it looks the task is brought op quite fast > after the interrupt fires so I think it is set at the wrong time, I'm > going to look into this. The I-pipe tracer has a trace point at the point where the timer was supposed to tick. -- Gilles. _______________________________________________ Xenomai-core mailing list Xenomaifirstname.lastname@example.org https://mail.gna.org/listinfo/xenomai-core