Module: xenomai-2.5
Branch: master
Commit: 74a196558cb30db8ac3ed5cf9bfd6e9e71e18122
URL:    
http://git.xenomai.org/?p=xenomai-2.5.git;a=commit;h=74a196558cb30db8ac3ed5cf9bfd6e9e71e18122

Author: Alexis Berlemont <alexis.berlem...@gmail.com>
Date:   Tue Jan 12 00:58:17 2010 +0100

analogy: [NI mite] add debug traces

---

 ksrc/drivers/analogy/national_instruments/mite.c |   65 ++++++++++++++--------
 1 files changed, 41 insertions(+), 24 deletions(-)

diff --git a/ksrc/drivers/analogy/national_instruments/mite.c 
b/ksrc/drivers/analogy/national_instruments/mite.c
index f812907..bec4a3c 100644
--- a/ksrc/drivers/analogy/national_instruments/mite.c
+++ b/ksrc/drivers/analogy/national_instruments/mite.c
@@ -105,22 +105,6 @@ static struct pci_driver mite_driver = {
        .remove = mite_remove,
 };
 
-static void dump_chip_signature(u32 csigr_bits)
-{
-       __a4l_info("MITE: version = %i, type = %i, mite mode = %i, "
-                  "interface mode = %i\n", 
-                  mite_csigr_version(csigr_bits), 
-                  mite_csigr_type(csigr_bits), 
-                  mite_csigr_mmode(csigr_bits), 
-                  mite_csigr_imode(csigr_bits));
-       __a4l_info("MITE: num channels = %i, write post fifo depth = %i, "
-                  "wins = %i, iowins = %i\n", 
-                  mite_csigr_dmac(csigr_bits), 
-                  mite_csigr_wpdep(csigr_bits), 
-                  mite_csigr_wins(csigr_bits), 
-                  mite_csigr_iowins(csigr_bits));
-}
-
 int mite_setup(struct mite_struct *mite, int use_iodwbsr_1)
 {
        unsigned long length;
@@ -129,6 +113,8 @@ int mite_setup(struct mite_struct *mite, int use_iodwbsr_1)
        u32 csigr_bits;
        unsigned unknown_dma_burst_bits;
 
+       __a4l_dbg(1, drv_dbg, "mite: starting setup...\n");
+
        if(pci_enable_device(mite->pcidev)){
                __a4l_err("error enabling mite\n");
                return -EIO;
@@ -152,9 +138,10 @@ int mite_setup(struct mite_struct *mite, int use_iodwbsr_1)
                return -ENOMEM;
        }
 
-       __a4l_info("MITE: 0x%08llx mapped to %p ",
-                  (unsigned long long)mite->mite_phys_addr, 
-                  mite->mite_io_addr);
+       __a4l_dbg(1, drv_dbg, 
+                 "mite: bar0(mite) 0x%08llx mapped to %p\n",
+                 (unsigned long long)mite->mite_phys_addr, 
+                 mite->mite_io_addr);
 
 
        /* The PCI BAR1 is the DAQ */
@@ -167,13 +154,17 @@ int mite_setup(struct mite_struct *mite, int 
use_iodwbsr_1)
                return -ENOMEM;
        }
 
-       __a4l_info("DAQ: 0x%08llx mapped to %p\n",
-                  (unsigned long long)mite->daq_phys_addr, 
-                  mite->daq_io_addr);
+       __a4l_dbg(1, drv_dbg, 
+                 "mite: bar0(daq) 0x%08llx mapped to %p\n",
+                 (unsigned long long)mite->daq_phys_addr, 
+                 mite->daq_io_addr);
 
        if (use_iodwbsr_1) {
+
+               __a4l_dbg(1, drv_dbg, 
+                         "mite: using I/O Window Base Size register 1\n");
+
                writel(0, mite->mite_io_addr + MITE_IODWBSR);
-               __a4l_err("MITE: using I/O Window Base Size register 1\n");
                writel(mite->
                       daq_phys_addr | WENAB |
                       MITE_IODWBSR_1_WSIZE_bits(length),
@@ -205,7 +196,20 @@ int mite_setup(struct mite_struct *mite, int use_iodwbsr_1)
                mite->num_channels = MAX_MITE_DMA_CHANNELS;
        }
 
-       dump_chip_signature(csigr_bits);
+       __a4l_dbg(1, drv_dbg,
+                 "mite: version = %i, type = %i, mite mode = %i, "
+                 "interface mode = %i\n", 
+                 mite_csigr_version(csigr_bits), 
+                 mite_csigr_type(csigr_bits), 
+                 mite_csigr_mmode(csigr_bits), 
+                 mite_csigr_imode(csigr_bits));
+       __a4l_dbg(1, drv_dbg,
+                 "mite: num channels = %i, write post fifo depth = %i, "
+                 "wins = %i, iowins = %i\n", 
+                 mite_csigr_dmac(csigr_bits), 
+                 mite_csigr_wpdep(csigr_bits), 
+                 mite_csigr_wins(csigr_bits), 
+                 mite_csigr_iowins(csigr_bits));
 
        for (i = 0; i < mite->num_channels; i++) {
                /* Registers the channel as a free one */
@@ -217,6 +221,8 @@ int mite_setup(struct mite_struct *mite, int use_iodwbsr_1)
                       CHCR_CLR_DONE_IE | CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE |
                       CHCR_CLR_LC_IE | CHCR_CLR_CONT_RB_IE,
                       mite->mite_io_addr + MITE_CHCR(i));
+
+               __a4l_dbg(1, drv_dbg, "mite: channel[%d] initialized\n", i);
        }
 
        mite->used = 1;
@@ -294,9 +300,20 @@ struct mite_channel *mite_request_channel_in_range(struct 
mite_struct *mite,
        unsigned long flags;
        struct mite_channel *channel = NULL;
 
+       __a4l_dbg(1, drv_dbg, 
+                 "mite: mite_request_channel_in_range: "
+                 "min_channel = %u, max_channel = %u\n", 
+                 min_channel, max_channel);
+
        /* spin lock so mite_release_channel can be called safely from 
interrupts */
        a4l_lock_irqsave(&mite->lock, flags);
        for (i = min_channel; i <= max_channel; ++i) {
+
+       __a4l_dbg(1, drv_dbg, 
+                 "mite: mite_request_channel_in_range: "
+                 "channel[%d] allocated = %d\n", 
+                 i, mite->channel_allocated[i]);
+
                if (mite->channel_allocated[i] == 0) {
                        mite->channel_allocated[i] = 1;
                        channel = &mite->channels[i];


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