Module: xenomai-2.5
Branch: master
Commit: b03bdec8c1941abe23180cd6ff038e03b153a007
URL:    
http://git.xenomai.org/?p=xenomai-2.5.git;a=commit;h=b03bdec8c1941abe23180cd6ff038e03b153a007

Author: Gilles Chanteperdrix <gilles.chanteperd...@xenomai.org>
Date:   Wed Jan 13 00:52:53 2010 +0100

arm: fix arith inline assembly for old versions of binutils

---

 include/asm-arm/arith.h |   24 ++++++++++++------------
 1 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/include/asm-arm/arith.h b/include/asm-arm/arith.h
index eca69ba..6908681 100644
--- a/include/asm-arm/arith.h
+++ b/include/asm-arm/arith.h
@@ -14,9 +14,9 @@ rthal_arm_nodiv_ullimd(const unsigned long long op,
 #else /* arm <= v3 */
 #define __rthal_add96and64(l0, l1, l2, s0, s1)         \
        do {                                            \
-               __asm__ ("adds %2, %4\n\t"              \
-                        "adcs %1, %3\n\t"              \
-                        "adc %0, #0\n\t"               \
+               __asm__ ("adds %2, %2, %4\n\t"          \
+                        "adcs %1, %1, %3\n\t"          \
+                        "adc %0, %0, #0\n\t"           \
                         : "+r"(l0), "+r"(l1), "+r"(l2) \
                         : "r"(s0), "r"(s1): "cc");     \
        } while (0)
@@ -46,17 +46,17 @@ rthal_arm_nodiv_ullimd(const unsigned long long op,
        
        __asm__ ("umull %[tl], %[rl], %[opl], %[fracl]\n\t"
                 "umull %[rm], %[rh], %[oph], %[frach]\n\t"
-                "adds %[rl], %[tl], lsr #31\n\t"
-                "adcs %[rm], #0\n\t"
-                "adc %[rh], #0\n\t"
+                "adds %[rl], %[rl], %[tl], lsr #31\n\t"
+                "adcs %[rm], %[rm], #0\n\t"
+                "adc %[rh], %[rh], #0\n\t"
                 "umull %[tl], %[th], %[oph], %[fracl]\n\t"
-                "adds %[rl], %[tl]\n\t"
-                "adcs %[rm], %[th]\n\t"
-                "adc %[rh], #0\n\t"
+                "adds %[rl], %[rl], %[tl]\n\t"
+                "adcs %[rm], %[rm], %[th]\n\t"
+                "adc %[rh], %[rh], #0\n\t"
                 "umull %[tl], %[th], %[opl], %[frach]\n\t"
-                "adds %[rl], %[tl]\n\t"
-                "adcs %[rm], %[th]\n\t"
-                "adc %[rh], #0\n\t"
+                "adds %[rl], %[rl], %[tl]\n\t"
+                "adcs %[rm], %[rm], %[th]\n\t"
+                "adc %[rh], %[rh], #0\n\t"
                 "umlal %[rm], %[rh], %[opl], %[integ]\n\t"
                 "mla %[rh], %[oph], %[integ], %[rh]\n\t"
                 : [rl]"=r"(rl), [rm]"=r"(rm), [rh]"=r"(rh),


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