Module: xenomai-head
Branch: master
Commit: e5e017db0837e9e4732932dc8a0ca6e8cc5d2606
URL:
http://git.xenomai.org/?p=xenomai-head.git;a=commit;h=e5e017db0837e9e4732932dc8a0ca6e8cc5d2606
Author: Gilles Chanteperdrix <gilles.chanteperd...@xenomai.org>
Date: Sun Aug 1 19:14:56 2010 +0200
arm: upgrade adeos patches to 2.6.30-1.15-02, 2.6.31-1.16-02, 2.6.33-1.17-02
---
....patch => adeos-ipipe-2.6.30-arm-1.15-03.patch} | 275 ++++++++++++-
....patch => adeos-ipipe-2.6.31-arm-1.16-02.patch} | 427 +++++++++++++++-----
....patch => adeos-ipipe-2.6.33-arm-1.17-02.patch} | 315 +++++++++++++--
3 files changed, 861 insertions(+), 156 deletions(-)
diff --git a/ksrc/arch/arm/patches/adeos-ipipe-2.6.30-arm-1.15-02.patch
b/ksrc/arch/arm/patches/adeos-ipipe-2.6.30-arm-1.15-03.patch
similarity index 98%
rename from ksrc/arch/arm/patches/adeos-ipipe-2.6.30-arm-1.15-02.patch
rename to ksrc/arch/arm/patches/adeos-ipipe-2.6.30-arm-1.15-03.patch
index 70b4925..3a114fd 100644
--- a/ksrc/arch/arm/patches/adeos-ipipe-2.6.30-arm-1.15-02.patch
+++ b/ksrc/arch/arm/patches/adeos-ipipe-2.6.30-arm-1.15-03.patch
@@ -466,7 +466,7 @@ index 0000000..28dc372
+#endif /* __ASM_ARM_FCSE_H */
diff --git a/arch/arm/include/asm/ipipe.h b/arch/arm/include/asm/ipipe.h
new file mode 100644
-index 0000000..7d9b735
+index 0000000..bb5cc43
--- /dev/null
+++ b/arch/arm/include/asm/ipipe.h
@@ -0,0 +1,274 @@
@@ -501,10 +501,10 @@ index 0000000..7d9b735
+#include <linux/ipipe_percpu.h>
+#include <mach/irqs.h> /* For __IPIPE_FEATURE_PIC_MUTE */
+
-+#define IPIPE_ARCH_STRING "1.15-02"
++#define IPIPE_ARCH_STRING "1.15-03"
+#define IPIPE_MAJOR_NUMBER 1
+#define IPIPE_MINOR_NUMBER 15
-+#define IPIPE_PATCH_NUMBER 2
++#define IPIPE_PATCH_NUMBER 3
+
+#ifdef CONFIG_SMP
+#error "I-pipe/arm: SMP not yet implemented"
@@ -4815,6 +4815,61 @@ index 1e93dfe..8374fa2 100644
+EXPORT_SYMBOL(__ipipe_mach_release_timer);
+
+#endif /* CONFIG_IPIPE */
+diff --git a/arch/arm/mach-ixp4xx/include/mach/platform.h
b/arch/arm/mach-ixp4xx/include/mach/platform.h
+index e824c02..126b297 100644
+--- a/arch/arm/mach-ixp4xx/include/mach/platform.h
++++ b/arch/arm/mach-ixp4xx/include/mach/platform.h
+@@ -72,8 +72,8 @@ extern unsigned long ixp4xx_exp_bus_size;
+ /*
+ * Clock Speed Definitions.
+ */
+-#define IXP4XX_PERIPHERAL_BUS_CLOCK (66) /* 66Mhzi APB BUS */
+-#define IXP4XX_UART_XTAL 14745600
++#define IXP4XX_PERIPHERAL_BUS_CLOCK (66) /* 66Mhzi APB BUS */
++#define IXP4XX_UART_XTAL 14745600
+
+ /*
+ * This structure provide a means for the board setup code
+@@ -138,7 +138,7 @@ extern struct pci_bus *ixp4xx_scan_bus(int nr, struct
pci_sys_data *sys);
+ */
+ /* GPIO pin types */
+ #define IXP4XX_GPIO_OUT 0x1
+-#define IXP4XX_GPIO_IN 0x2
++#define IXP4XX_GPIO_IN 0x2
+
+ /* GPIO signal types */
+ #define IXP4XX_GPIO_LOW 0
+@@ -150,10 +150,14 @@ extern struct pci_bus *ixp4xx_scan_bus(int nr, struct
pci_sys_data *sys);
+
+ static inline void gpio_line_config(u8 line, u32 direction)
+ {
++ unsigned long flags;
++
++ local_irq_save_hw(flags);
+ if (direction == IXP4XX_GPIO_IN)
+ *IXP4XX_GPIO_GPOER |= (1 << line);
+ else
+ *IXP4XX_GPIO_GPOER &= ~(1 << line);
++ local_irq_restore_hw(flags);
+ }
+
+ static inline void gpio_line_get(u8 line, int *value)
+@@ -163,11 +167,14 @@ static inline void gpio_line_get(u8 line, int *value)
+
+ static inline void gpio_line_set(u8 line, int value)
+ {
++ unsigned long flags;
++
++ local_irq_save_hw(flags);
+ if (value == IXP4XX_GPIO_HIGH)
+ *IXP4XX_GPIO_GPOUTR |= (1 << line);
+ else if (value == IXP4XX_GPIO_LOW)
+ *IXP4XX_GPIO_GPOUTR &= ~(1 << line);
++ local_irq_restore_hw(flags);
+ }
+
+ #endif // __ASSEMBLY__
+-
diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c
index 380be0c..28a8c3c 100644
--- a/arch/arm/mach-mx3/devices.c
@@ -5495,6 +5550,35 @@ index 63c5ab6..089b68f 100644
}
}
}
+diff --git a/arch/arm/mach-sa1100/gpio.c b/arch/arm/mach-sa1100/gpio.c
+index 0d3829a..873f883 100644
+--- a/arch/arm/mach-sa1100/gpio.c
++++ b/arch/arm/mach-sa1100/gpio.c
+@@ -32,9 +32,9 @@ static int sa1100_direction_input(struct gpio_chip *chip,
unsigned offset)
+ {
+ unsigned long flags;
+
+- local_irq_save(flags);
++ local_irq_save_hw(flags);
+ GPDR &= ~GPIO_GPIO(offset);
+- local_irq_restore(flags);
++ local_irq_restore_hw(flags);
+ return 0;
+ }
+
+@@ -42,10 +42,10 @@ static int sa1100_direction_output(struct gpio_chip *chip,
unsigned offset, int
+ {
+ unsigned long flags;
+
+- local_irq_save(flags);
++ local_irq_save_hw(flags);
+ sa1100_gpio_set(chip, offset, value);
+ GPDR |= GPIO_GPIO(offset);
+- local_irq_restore(flags);
++ local_irq_restore_hw(flags);
+ return 0;
+ }
+
diff --git a/arch/arm/mach-sa1100/irq.c b/arch/arm/mach-sa1100/irq.c
index 3093d46..04a56d2 100644
--- a/arch/arm/mach-sa1100/irq.c
@@ -6461,7 +6545,7 @@ index 386e0d5..0bb140e 100644
+}
+#endif /* CONFIG_IPIPE */
diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c
-index 89e9579..9190e1e 100644
+index 89e9579..54f1ae5 100644
--- a/arch/arm/plat-mxc/gpio.c
+++ b/arch/arm/plat-mxc/gpio.c
@@ -25,6 +25,13 @@
@@ -6478,7 +6562,29 @@ index 89e9579..9190e1e 100644
static struct mxc_gpio_port *mxc_gpio_ports;
static int gpio_table_size;
-@@ -110,8 +117,7 @@ static void mxc_gpio_irq_handler(struct mxc_gpio_port
*port, u32 irq_stat)
+@@ -68,6 +75,7 @@ static int gpio_set_irq_type(u32 irq, u32 type)
+ {
+ u32 gpio = irq_to_gpio(irq);
+ struct mxc_gpio_port *port = &mxc_gpio_ports[gpio / 32];
++ unsigned long flags;
+ u32 bit, val;
+ int edge;
+ void __iomem *reg = port->base;
+@@ -89,11 +97,13 @@ static int gpio_set_irq_type(u32 irq, u32 type)
+ return -EINVAL;
+ }
+
++ spin_lock_irqsave(&port->lock, flags);
+ reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
+ bit = gpio & 0xf;
+ val = __raw_readl(reg) & ~(0x3 << (bit << 1));
+ __raw_writel(val | (edge << (bit << 1)), reg);
+ _clear_gpio_irqstatus(port, gpio & 0x1f);
++ spin_unlock_irqrestore(&port->lock, flags);
+
+ return 0;
+ }
+@@ -110,8 +120,7 @@ static void mxc_gpio_irq_handler(struct mxc_gpio_port
*port, u32 irq_stat)
continue;
BUG_ON(!(irq_desc[gpio_irq_no].handle_irq));
@@ -6488,7 +6594,7 @@ index 89e9579..9190e1e 100644
}
}
-@@ -127,7 +133,7 @@ static void mx3_gpio_irq_handler(u32 irq, struct irq_desc
*desc)
+@@ -127,7 +136,7 @@ static void mx3_gpio_irq_handler(u32 irq, struct irq_desc
*desc)
mxc_gpio_irq_handler(port, irq_stat);
}
@@ -6497,7 +6603,7 @@ index 89e9579..9190e1e 100644
#ifdef CONFIG_ARCH_MX2
/* MX2 has one interrupt *for all* gpio ports */
-@@ -148,7 +154,7 @@ static void mx2_gpio_irq_handler(u32 irq, struct irq_desc
*desc)
+@@ -148,7 +157,7 @@ static void mx2_gpio_irq_handler(u32 irq, struct irq_desc
*desc)
mxc_gpio_irq_handler(&port[i], irq_stat);
}
}
@@ -6506,7 +6612,39 @@ index 89e9579..9190e1e 100644
static struct irq_chip gpio_irq_chip = {
.ack = gpio_ack_irq,
-@@ -222,7 +228,11 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int
cnt)
+@@ -162,14 +171,17 @@ static void _set_gpio_direction(struct gpio_chip *chip,
unsigned offset,
+ {
+ struct mxc_gpio_port *port =
+ container_of(chip, struct mxc_gpio_port, chip);
++ unsigned long flags;
+ u32 l;
+
++ spin_lock_irqsave(&port->lock, flags);
+ l = __raw_readl(port->base + GPIO_GDIR);
+ if (dir)
+ l |= 1 << offset;
+ else
+ l &= ~(1 << offset);
+ __raw_writel(l, port->base + GPIO_GDIR);
++ spin_unlock_irqrestore(&port->lock, flags);
+ }
+
+ static void mxc_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
+@@ -177,10 +189,13 @@ static void mxc_gpio_set(struct gpio_chip *chip,
unsigned offset, int value)
+ struct mxc_gpio_port *port =
+ container_of(chip, struct mxc_gpio_port, chip);
+ void __iomem *reg = port->base + GPIO_DR;
++ unsigned long flags;
+ u32 l;
+
++ spin_lock_irqsave(&port->lock, flags);
+ l = (__raw_readl(reg) & (~(1 << offset))) | (value << offset);
+ __raw_writel(l, reg);
++ spin_unlock_irqrestore(&port->lock, flags);
+ }
+
+ static int mxc_gpio_get(struct gpio_chip *chip, unsigned offset)
+@@ -222,7 +237,11 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int
cnt)
for (j = port[i].virtual_irq_start;
j < port[i].virtual_irq_start + 32; j++) {
set_irq_chip(j, &gpio_irq_chip);
@@ -6518,6 +6656,14 @@ index 89e9579..9190e1e 100644
set_irq_flags(j, IRQF_VALID);
}
+@@ -233,6 +252,7 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int
cnt)
+ port[i].chip.set = mxc_gpio_set;
+ port[i].chip.base = i * 32;
+ port[i].chip.ngpio = 32;
++ spin_lock_init(&port[i].lock);
+
+ /* its a serious configuration bug when it fails */
+ BUG_ON( gpiochip_add(&port[i].chip) < 0 );
diff --git a/arch/arm/plat-mxc/include/mach/common.h
b/arch/arm/plat-mxc/include/mach/common.h
index b2f9b72..e598ec6 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
@@ -6531,6 +6677,18 @@ index b2f9b72..e598ec6 100644
+#endif
+
#endif
+diff --git a/arch/arm/plat-mxc/include/mach/gpio.h
b/arch/arm/plat-mxc/include/mach/gpio.h
+index ea509f1..a125b92 100644
+--- a/arch/arm/plat-mxc/include/mach/gpio.h
++++ b/arch/arm/plat-mxc/include/mach/gpio.h
+@@ -35,6 +35,7 @@ struct mxc_gpio_port {
+ int irq;
+ int virtual_irq_start;
+ struct gpio_chip chip;
++ ipipe_spinlock_t lock;
+ };
+
+ int mxc_gpio_init(struct mxc_gpio_port*, int);
diff --git a/arch/arm/plat-mxc/time.c b/arch/arm/plat-mxc/time.c
index dab3357..6d855f8 100644
--- a/arch/arm/plat-mxc/time.c
@@ -6755,7 +6913,7 @@ index 55bb996..d546288 100644
/**
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
-index ee0b21f..4675f00 100644
+index ee0b21f..406601f 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -17,6 +17,7 @@
@@ -6766,6 +6924,15 @@ index ee0b21f..4675f00 100644
#include <linux/io.h>
#include <mach/hardware.h>
+@@ -166,7 +167,7 @@ struct gpio_bank {
+ u32 saved_risingdetect;
+ #endif
+ u32 level_mask;
+- spinlock_t lock;
++ ipipe_spinlock_t lock;
+ struct gpio_chip chip;
+ struct clk *dbck;
+ };
@@ -1111,7 +1112,7 @@ static void gpio_irq_handler(unsigned int irq, struct
irq_desc *desc)
if (!(isr & 1))
continue;
@@ -6790,7 +6957,7 @@ index 20f1054..42a0b8d 100644
u32 omap_dm_timer_modify_idlect_mask(u32 inputmask);
struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer);
diff --git a/arch/arm/plat-pxa/gpio.c b/arch/arm/plat-pxa/gpio.c
-index abc79d4..caaf694 100644
+index abc79d4..6845d84 100644
--- a/arch/arm/plat-pxa/gpio.c
+++ b/arch/arm/plat-pxa/gpio.c
@@ -17,6 +17,7 @@
@@ -6801,6 +6968,15 @@ index abc79d4..caaf694 100644
#include <mach/gpio.h>
+@@ -39,7 +40,7 @@ struct pxa_gpio_chip {
+ #endif
+ };
+
+-static DEFINE_SPINLOCK(gpio_lock);
++static IPIPE_DEFINE_SPINLOCK(gpio_lock);
+ static struct pxa_gpio_chip *pxa_gpio_chips;
+
+ #define for_each_gpio_chip(i, c) \
@@ -225,7 +226,7 @@ static void pxa_gpio_demux_handler(unsigned int irq,
struct irq_desc *desc)
while (n < BITS_PER_LONG) {
loop = 1;
@@ -6819,6 +6995,72 @@ index abc79d4..caaf694 100644
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
+diff --git a/arch/arm/plat-s3c/gpio.c b/arch/arm/plat-s3c/gpio.c
+index d71dd6d..7f70457 100644
+--- a/arch/arm/plat-s3c/gpio.c
++++ b/arch/arm/plat-s3c/gpio.c
+@@ -39,7 +39,7 @@ static __init void s3c_gpiolib_track(struct s3c_gpio_chip
*chip)
+ * chip is as following:
+ *
+ * base + 0x00: Control register, 2 bits per gpio
+- * gpio n: 2 bits starting at (2*n)
++ * gpio n: 2 bits starting at (2*n)
+ * 00 = input, 01 = output, others mean special-function
+ * base + 0x04: Data register, 1 bit per gpio
+ * bit n: data bit n
+@@ -52,14 +52,14 @@ static int s3c_gpiolib_input(struct gpio_chip *chip,
unsigned offset)
+ unsigned long flags;
+ unsigned long con;
+
+- local_irq_save(flags);
++ local_irq_save_hw(flags);
+
+ con = __raw_readl(base + 0x00);
+ con &= ~(3 << (offset * 2));
+
+ __raw_writel(con, base + 0x00);
+
+- local_irq_restore(flags);
++ local_irq_restore_hw(flags);
+ return 0;
+ }
+
+@@ -72,7 +72,7 @@ static int s3c_gpiolib_output(struct gpio_chip *chip,
+ unsigned long dat;
+ unsigned long con;
+
+- local_irq_save(flags);
++ local_irq_save_hw(flags);
+
+ dat = __raw_readl(base + 0x04);
+ dat &= ~(1 << offset);
+@@ -87,7 +87,7 @@ static int s3c_gpiolib_output(struct gpio_chip *chip,
+ __raw_writel(con, base + 0x00);
+ __raw_writel(dat, base + 0x04);
+
+- local_irq_restore(flags);
++ local_irq_restore_hw(flags);
+ return 0;
+ }
+
+@@ -99,7 +99,7 @@ static void s3c_gpiolib_set(struct gpio_chip *chip,
+ unsigned long flags;
+ unsigned long dat;
+
+- local_irq_save(flags);
++ local_irq_save_hw(flags);
+
+ dat = __raw_readl(base + 0x04);
+ dat &= ~(1 << offset);
+@@ -107,7 +107,7 @@ static void s3c_gpiolib_set(struct gpio_chip *chip,
+ dat |= 1 << offset;
+ __raw_writel(dat, base + 0x04);
+
+- local_irq_restore(flags);
++ local_irq_restore_hw(flags);
+ }
+
+ static int s3c_gpiolib_get(struct gpio_chip *chip, unsigned offset)
diff --git a/arch/arm/plat-s3c/time.c b/arch/arm/plat-s3c/time.c
index 3b27b29..976fe03 100644
--- a/arch/arm/plat-s3c/time.c
@@ -7405,6 +7647,19 @@ index 01599c4..abe06aa 100644
return NOTIFY_DONE;
}
+diff --git a/drivers/mfd/twl4030-irq.c b/drivers/mfd/twl4030-irq.c
+index aca2670..4885bcc 100644
+--- a/drivers/mfd/twl4030-irq.c
++++ b/drivers/mfd/twl4030-irq.c
+@@ -235,7 +235,7 @@ static int twl4030_irq_thread(void *data)
+ note_interrupt(module_irq, d,
+ IRQ_NONE);
+ else
+- d->handle_irq(module_irq, d);
++ ipipe_handle_irq_cond(module_irq);
+ }
+ }
+ local_irq_enable();
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 6d1ac18..c028337 100644
--- a/drivers/misc/Kconfig
diff --git a/ksrc/arch/arm/patches/adeos-ipipe-2.6.31-arm-1.16-01.patch
b/ksrc/arch/arm/patches/adeos-ipipe-2.6.31-arm-1.16-02.patch
similarity index 97%
rename from ksrc/arch/arm/patches/adeos-ipipe-2.6.31-arm-1.16-01.patch
rename to ksrc/arch/arm/patches/adeos-ipipe-2.6.31-arm-1.16-02.patch
index 4803be3..bea3d4a 100644
--- a/ksrc/arch/arm/patches/adeos-ipipe-2.6.31-arm-1.16-01.patch
+++ b/ksrc/arch/arm/patches/adeos-ipipe-2.6.31-arm-1.16-02.patch
@@ -620,7 +620,7 @@ index 0000000..4e39a8c
+#endif /* __ASM_ARM_FCSE_H */
diff --git a/arch/arm/include/asm/ipipe.h b/arch/arm/include/asm/ipipe.h
new file mode 100644
-index 0000000..8ae0cb3
+index 0000000..d6fc908
--- /dev/null
+++ b/arch/arm/include/asm/ipipe.h
@@ -0,0 +1,274 @@
@@ -655,10 +655,10 @@ index 0000000..8ae0cb3
+#include <linux/ipipe_percpu.h>
+#include <mach/irqs.h> /* For __IPIPE_FEATURE_PIC_MUTE */
+
-+#define IPIPE_ARCH_STRING "1.16-01"
++#define IPIPE_ARCH_STRING "1.16-02"
+#define IPIPE_MAJOR_NUMBER 1
+#define IPIPE_MINOR_NUMBER 16
-+#define IPIPE_PATCH_NUMBER 1
++#define IPIPE_PATCH_NUMBER 2
+
+#ifdef CONFIG_SMP
+#error "I-pipe/arm: SMP not yet implemented"
@@ -815,8 +815,8 @@ index 0000000..8ae0cb3
+#else /* __IPIPE_FEATURE_PIC_MUTE */
+
+typedef unsigned long
-+__ipipe_irqbits_t[(NR_IRQS + BITS_PER_LONG - 1) / BITS_PER_LONG];
-+extern __ipipe_irqbits_t __ipipe_irqbits;
++__ipipe_root_irqmap_t[(NR_IRQS + BITS_PER_LONG - 1) / BITS_PER_LONG];
++extern __ipipe_root_irqmap_t __ipipe_root_irqmap;
+
+void __ipipe_disable_irqdesc(struct ipipe_domain *ipd, unsigned irq);
+
@@ -2671,10 +2671,10 @@ index 0000000..1b9550c
+#endif /* CONFIG_ARM_FCSE_MESSAGES */
diff --git a/arch/arm/kernel/ipipe.c b/arch/arm/kernel/ipipe.c
new file mode 100644
-index 0000000..0ed37e4
+index 0000000..7d160bf
--- /dev/null
+++ b/arch/arm/kernel/ipipe.c
-@@ -0,0 +1,533 @@
+@@ -0,0 +1,534 @@
+/* -*- linux-c -*-
+ * linux/arch/arm/kernel/ipipe.c
+ *
@@ -2726,8 +2726,8 @@ index 0000000..0ed37e4
+DEFINE_PER_CPU(struct mm_struct *,ipipe_active_mm);
+EXPORT_PER_CPU_SYMBOL(ipipe_active_mm);
+#ifdef __IPIPE_FEATURE_PIC_MUTE
-+__ipipe_irqbits_t __ipipe_irqbits;
-+IPIPE_DEFINE_SPINLOCK(__ipipe_irqbits_lock);
++__ipipe_root_irqmap_t __ipipe_root_irqmap;
++IPIPE_DEFINE_SPINLOCK(__ipipe_root_irqmap_lock);
+#endif /* __IPIPE_FEATURE_PIC_MUTE */
+
+extern struct irq_desc irq_desc[];
@@ -2803,7 +2803,7 @@ index 0000000..0ed37e4
+ info->cpufreq = ipipe_cpu_freq();
+ info->archdep.tmirq = __ipipe_mach_timerint;
+ info->archdep.tmfreq = info->cpufreq;
-+ __ipipe_mach_get_tscinfo(&info->archdep.tsc);
++ __ipipe_mach_get_tscinfo(&info->archdep.tsc);
+
+ return 0;
+}
@@ -2827,10 +2827,11 @@ index 0000000..0ed37e4
+#ifdef __IPIPE_FEATURE_PIC_MUTE
+ if (ipd == &ipipe_root)
+ return;
-+
-+ spin_lock_irqsave(&__ipipe_irqbits_lock, flags);
-+ __ipipe_irqbits[irq / BITS_PER_LONG] &= ~(1 << (irq % BITS_PER_LONG));
-+ spin_unlock_irqrestore(&__ipipe_irqbits_lock, flags);
++
++ spin_lock_irqsave(&__ipipe_root_irqmap_lock, flags);
++ __ipipe_root_irqmap
++ [irq / BITS_PER_LONG] &= ~(1 << (irq % BITS_PER_LONG));
++ spin_unlock_irqrestore(&__ipipe_root_irqmap_lock, flags);
+#else
+ (void) flags;
+#endif /* __IPIPE_FEATURE_PIC_MUTE */
@@ -2844,10 +2845,10 @@ index 0000000..0ed37e4
+
+ if (ipd == &ipipe_root)
+ return;
-+
-+ spin_lock_irqsave(&__ipipe_irqbits_lock, flags);
-+ __ipipe_irqbits[irq / BITS_PER_LONG] |= 1 << (irq % BITS_PER_LONG);
-+ spin_unlock_irqrestore(&__ipipe_irqbits_lock, flags);
++
++ spin_lock_irqsave(&__ipipe_root_irqmap_lock, flags);
++ __ipipe_root_irqmap[irq / BITS_PER_LONG] |= 1 << (irq % BITS_PER_LONG);
++ spin_unlock_irqrestore(&__ipipe_root_irqmap_lock, flags);
+}
+EXPORT_SYMBOL(__ipipe_disable_irqdesc);
+EXPORT_SYMBOL(ipipe_mute_pic);
@@ -2994,21 +2995,21 @@ index 0000000..0ed37e4
+
+asmlinkage int __ipipe_check_root_interruptible(void)
+{
-+ return ipipe_root_domain_p && !__ipipe_test_root();
++ return ipipe_root_domain_p && !__ipipe_test_root();
+}
+
-+__kprobes int
++__kprobes int
+__ipipe_switch_to_notifier_call_chain(struct atomic_notifier_head *nh,
+ unsigned long val, void *v)
+{
-+ unsigned long flags;
-+ int rc;
++ unsigned long flags;
++ int rc;
+
-+ local_irq_save(flags);
-+ rc = atomic_notifier_call_chain(nh, val, v);
-+ __local_irq_restore_nosync(flags);
++ local_irq_save(flags);
++ rc = atomic_notifier_call_chain(nh, val, v);
++ __local_irq_restore_nosync(flags);
+
-+ return rc;
++ return rc;
+}
+
+asmlinkage int __ipipe_syscall_root(unsigned long scno, struct pt_regs *regs)
@@ -3072,16 +3073,16 @@ index 0000000..0ed37e4
+
+ if (test_bit(IPIPE_STICKY_FLAG, &this_domain->irqs[irq].control))
+ head = &this_domain->p_link;
-+ else {
-+ head = __ipipe_pipeline.next;
-+ next_domain = list_entry(head, struct ipipe_domain, p_link);
-+ if (likely(test_bit(IPIPE_WIRED_FLAG,
&next_domain->irqs[irq].control))) {
-+ if (!m_ack && next_domain->irqs[irq].acknowledge !=
NULL)
-+ next_domain->irqs[irq].acknowledge(irq,
irq_desc + irq);
-+ __ipipe_dispatch_wired(next_domain, irq);
-+ goto finalize_nosync;
-+ }
-+ }
++ else {
++ head = __ipipe_pipeline.next;
++ next_domain = list_entry(head, struct ipipe_domain, p_link);
++ if (likely(test_bit(IPIPE_WIRED_FLAG,
&next_domain->irqs[irq].control))) {
++ if (!m_ack && next_domain->irqs[irq].acknowledge !=
NULL)
++ next_domain->irqs[irq].acknowledge(irq,
irq_desc + irq);
++ __ipipe_dispatch_wired(next_domain, irq);
++ goto finalize_nosync;
++ }
++ }
+
+ /* Ack the interrupt. */
+
@@ -3105,9 +3106,9 @@ index 0000000..0ed37e4
+ __ipipe_set_irq_pending(next_domain, irq);
+
+ if (!m_ack && next_domain->irqs[irq].acknowledge) {
-+ next_domain->irqs[irq].acknowledge(irq,
irq_desc + irq);
-+ m_ack = 1;
-+ }
++ next_domain->irqs[irq].acknowledge(irq,
irq_desc + irq);
++ m_ack = 1;
++ }
+ }
+
+ /*
@@ -3141,8 +3142,8 @@ index 0000000..0ed37e4
+ __ipipe_walk_pipeline(head);
+
+finalize_nosync:
-+ if (!ipipe_root_domain_p || __ipipe_test_root())
-+ return 0;
++ if (!ipipe_root_domain_p || __ipipe_test_root())
++ return 0;
+
+#ifdef CONFIG_SMP
+ /*
@@ -3150,34 +3151,34 @@ index 0000000..0ed37e4
+ * preemptible kernels along the way out through
+ * ret_from_intr.
+ */
-+ if (!regs)
-+ __set_bit(IPIPE_STALL_FLAG, &ipipe_root_cpudom_var(status));
++ if (!regs)
++ __set_bit(IPIPE_STALL_FLAG, &ipipe_root_cpudom_var(status));
+#endif /* CONFIG_SMP */
+
-+ return 1;
++ return 1;
+}
+
+asmlinkage int __ipipe_grab_irq(int irq, struct pt_regs *regs)
+{
-+ int status;
++ int status;
+
+#ifdef irq_finish
+ /* AT91 specific workaround */
-+ irq_finish(irq);
++ irq_finish(irq);
+#endif /* irq_finish */
+
+ if (irq == __ipipe_mach_timerint) {
-+ /*
++ /*
+ * Given our deferred dispatching model for regular IRQs, we
-+ * only record CPU regs for the last timer interrupt, so that
-+ * the timer handler charges CPU times properly. It is assumed
-+ * that other interrupt handlers don't actually care for such
-+ * information.
++ * only record CPU regs for the last timer interrupt, so that
++ * the timer handler charges CPU times properly. It is assumed
++ * that other interrupt handlers don't actually care for such
++ * information.
+ */
+ __raw_get_cpu_var(__ipipe_tick_regs).ARM_cpsr =
-+ (ipipe_root_domain_p
-+ ? regs->ARM_cpsr
-+ : regs->ARM_cpsr | PSR_I_BIT);
++ (ipipe_root_domain_p
++ ? regs->ARM_cpsr
++ : regs->ARM_cpsr | PSR_I_BIT);
+ __raw_get_cpu_var(__ipipe_tick_regs).ARM_pc = regs->ARM_pc;
+ }
+
@@ -3191,7 +3192,7 @@ index 0000000..0ed37e4
+ ipipe_trace_end(regs->ARM_ORIG_r0);
+#endif
+
-+ return status;
++ return status;
+}
+
+EXPORT_SYMBOL_GPL(show_stack);
@@ -4173,7 +4174,7 @@ index 211c5c1..9cdad31 100644
void __init at91sam9rl_init_interrupts(unsigned int priority[NR_AIC_IRQS])
diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c
-index f2236f0..e653ab3 100644
+index f2236f0..52617ad 100644
--- a/arch/arm/mach-at91/gpio.c
+++ b/arch/arm/mach-at91/gpio.c
@@ -25,6 +25,13 @@
@@ -4184,7 +4185,7 @@ index f2236f0..e653ab3 100644
+#include <asm/irq.h>
+
+#ifdef __IPIPE_FEATURE_PIC_MUTE
-+DEFINE_PER_CPU(__ipipe_irqbits_t, __ipipe_muted_irqs);
++DEFINE_PER_CPU(__ipipe_root_irqmap_t, __ipipe_muted_irqs);
+#endif /* __IPIPE_FEATURE_PIC_MUTE */
+#endif /* CONFIG_IPIPE */
@@ -4222,13 +4223,13 @@ index f2236f0..e653ab3 100644
+
+ for (i = 0; i < gpio_banks; i++) {
+ unmasked = __raw_readl(gpio_chip[i].regbase + PIO_IMR);
-+ muted = unmasked & __ipipe_irqbits[i + 1];
++ muted = unmasked & __ipipe_root_irqmap[i + 1];
+ __raw_get_cpu_var(__ipipe_muted_irqs)[i + 1] = muted;
+ __raw_writel(muted, gpio_chip[i].regbase + PIO_IDR);
+ }
+
+ unmasked = at91_sys_read(AT91_AIC_IMR);
-+ muted = unmasked & __ipipe_irqbits[0];
++ muted = unmasked & __ipipe_root_irqmap[0];
+ __raw_get_cpu_var(__ipipe_muted_irqs)[0] = muted;
+ at91_sys_write(AT91_AIC_IDCR, muted);
+}
@@ -4254,7 +4255,7 @@ index f2236f0..e653ab3 100644
struct at91_gpio_chip *this, *prev;
+#if defined(CONFIG_IPIPE) && defined(__IPIPE_FEATURE_PIC_MUTE)
-+ memset(__ipipe_irqbits, ~0, sizeof(__ipipe_irqbits));
++ memset(__ipipe_root_irqmap, ~0, sizeof(__ipipe_root_irqmap));
+#endif /* CONFIG_IPIPE && __IPIPE_FEATURE_PIC_MUTE */
+
for (pioc = 0, pin = PIN_BASE, this = gpio_chip, prev = NULL;
@@ -4265,7 +4266,7 @@ index f2236f0..e653ab3 100644
set_irq_chip_data(id, this);
set_irq_chained_handler(id, gpio_irq_handler);
+#if defined(CONFIG_IPIPE) && defined(__IPIPE_FEATURE_PIC_MUTE)
-+ __ipipe_irqbits[0] &= ~(1 << id);
++ __ipipe_root_irqmap[0] &= ~(1 << id);
+#endif /* CONFIG_IPIPE && __IPIPE_FEATURE_PIC_MUTE */
}
pr_info("AT91: %d gpio irqs in %d banks\n", pin - PIN_BASE, gpio_banks);
@@ -4926,6 +4927,61 @@ index 1e93dfe..8374fa2 100644
+EXPORT_SYMBOL(__ipipe_mach_release_timer);
+
+#endif /* CONFIG_IPIPE */
+diff --git a/arch/arm/mach-ixp4xx/include/mach/platform.h
b/arch/arm/mach-ixp4xx/include/mach/platform.h
+index e824c02..126b297 100644
+--- a/arch/arm/mach-ixp4xx/include/mach/platform.h
++++ b/arch/arm/mach-ixp4xx/include/mach/platform.h
+@@ -72,8 +72,8 @@ extern unsigned long ixp4xx_exp_bus_size;
+ /*
+ * Clock Speed Definitions.
+ */
+-#define IXP4XX_PERIPHERAL_BUS_CLOCK (66) /* 66Mhzi APB BUS */
+-#define IXP4XX_UART_XTAL 14745600
++#define IXP4XX_PERIPHERAL_BUS_CLOCK (66) /* 66Mhzi APB BUS */
++#define IXP4XX_UART_XTAL 14745600
+
+ /*
+ * This structure provide a means for the board setup code
+@@ -138,7 +138,7 @@ extern struct pci_bus *ixp4xx_scan_bus(int nr, struct
pci_sys_data *sys);
+ */
+ /* GPIO pin types */
+ #define IXP4XX_GPIO_OUT 0x1
+-#define IXP4XX_GPIO_IN 0x2
++#define IXP4XX_GPIO_IN 0x2
+
+ /* GPIO signal types */
+ #define IXP4XX_GPIO_LOW 0
+@@ -150,10 +150,14 @@ extern struct pci_bus *ixp4xx_scan_bus(int nr, struct
pci_sys_data *sys);
+
+ static inline void gpio_line_config(u8 line, u32 direction)
+ {
++ unsigned long flags;
++
++ local_irq_save_hw(flags);
+ if (direction == IXP4XX_GPIO_IN)
+ *IXP4XX_GPIO_GPOER |= (1 << line);
+ else
+ *IXP4XX_GPIO_GPOER &= ~(1 << line);
++ local_irq_restore_hw(flags);
+ }
+
+ static inline void gpio_line_get(u8 line, int *value)
+@@ -163,11 +167,14 @@ static inline void gpio_line_get(u8 line, int *value)
+
+ static inline void gpio_line_set(u8 line, int value)
+ {
++ unsigned long flags;
++
++ local_irq_save_hw(flags);
+ if (value == IXP4XX_GPIO_HIGH)
+ *IXP4XX_GPIO_GPOUTR |= (1 << line);
+ else if (value == IXP4XX_GPIO_LOW)
+ *IXP4XX_GPIO_GPOUTR &= ~(1 << line);
++ local_irq_restore_hw(flags);
+ }
+
+ #endif // __ASSEMBLY__
+-
diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c
index 9e87e08..f17b98c 100644
--- a/arch/arm/mach-mx3/devices.c
@@ -5653,6 +5709,35 @@ index 63c5ab6..089b68f 100644
}
}
}
+diff --git a/arch/arm/mach-sa1100/gpio.c b/arch/arm/mach-sa1100/gpio.c
+index 0d3829a..873f883 100644
+--- a/arch/arm/mach-sa1100/gpio.c
++++ b/arch/arm/mach-sa1100/gpio.c
+@@ -32,9 +32,9 @@ static int sa1100_direction_input(struct gpio_chip *chip,
unsigned offset)
+ {
+ unsigned long flags;
+
+- local_irq_save(flags);
++ local_irq_save_hw(flags);
+ GPDR &= ~GPIO_GPIO(offset);
+- local_irq_restore(flags);
++ local_irq_restore_hw(flags);
+ return 0;
+ }
+
+@@ -42,10 +42,10 @@ static int sa1100_direction_output(struct gpio_chip *chip,
unsigned offset, int
+ {
+ unsigned long flags;
+
+- local_irq_save(flags);
++ local_irq_save_hw(flags);
+ sa1100_gpio_set(chip, offset, value);
+ GPDR |= GPIO_GPIO(offset);
+- local_irq_restore(flags);
++ local_irq_restore_hw(flags);
+ return 0;
+ }
+
diff --git a/arch/arm/mach-sa1100/irq.c b/arch/arm/mach-sa1100/irq.c
index 3093d46..04a56d2 100644
--- a/arch/arm/mach-sa1100/irq.c
@@ -6728,7 +6813,7 @@ index 386e0d5..0bb140e 100644
+}
+#endif /* CONFIG_IPIPE */
diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c
-index 7506d96..4f712db 100644
+index 7506d96..6b00a32 100644
--- a/arch/arm/plat-mxc/gpio.c
+++ b/arch/arm/plat-mxc/gpio.c
@@ -25,6 +25,13 @@
@@ -6745,7 +6830,29 @@ index 7506d96..4f712db 100644
static struct mxc_gpio_port *mxc_gpio_ports;
static int gpio_table_size;
-@@ -157,8 +164,7 @@ static void mxc_gpio_irq_handler(struct mxc_gpio_port
*port, u32 irq_stat)
+@@ -70,6 +77,7 @@ static int gpio_set_irq_type(u32 irq, u32 type)
+ {
+ u32 gpio = irq_to_gpio(irq);
+ struct mxc_gpio_port *port = &mxc_gpio_ports[gpio / 32];
++ unsigned long flags;
+ u32 bit, val;
+ int edge;
+ void __iomem *reg = port->base;
+@@ -103,11 +111,13 @@ static int gpio_set_irq_type(u32 irq, u32 type)
+ return -EINVAL;
+ }
+
++ spin_lock_irqsave(&port->lock, flags);
+ reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
+ bit = gpio & 0xf;
+ val = __raw_readl(reg) & ~(0x3 << (bit << 1));
+ __raw_writel(val | (edge << (bit << 1)), reg);
+ _clear_gpio_irqstatus(port, gpio & 0x1f);
++ spin_unlock_irqrestore(&port->lock, flags);
+
+ return 0;
+ }
+@@ -157,8 +167,7 @@ static void mxc_gpio_irq_handler(struct mxc_gpio_port
*port, u32 irq_stat)
if (port->both_edges & (1 << (gpio & 31)))
mxc_flip_edge(port, gpio);
@@ -6755,7 +6862,7 @@ index 7506d96..4f712db 100644
}
}
-@@ -174,7 +180,7 @@ static void mx3_gpio_irq_handler(u32 irq, struct irq_desc
*desc)
+@@ -174,7 +183,7 @@ static void mx3_gpio_irq_handler(u32 irq, struct irq_desc
*desc)
mxc_gpio_irq_handler(port, irq_stat);
}
@@ -6764,7 +6871,7 @@ index 7506d96..4f712db 100644
#ifdef CONFIG_ARCH_MX2
/* MX2 has one interrupt *for all* gpio ports */
-@@ -195,7 +201,7 @@ static void mx2_gpio_irq_handler(u32 irq, struct irq_desc
*desc)
+@@ -195,7 +204,7 @@ static void mx2_gpio_irq_handler(u32 irq, struct irq_desc
*desc)
mxc_gpio_irq_handler(&port[i], irq_stat);
}
}
@@ -6773,7 +6880,39 @@ index 7506d96..4f712db 100644
static struct irq_chip gpio_irq_chip = {
.ack = gpio_ack_irq,
-@@ -269,7 +275,11 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int
cnt)
+@@ -209,14 +218,17 @@ static void _set_gpio_direction(struct gpio_chip *chip,
unsigned offset,
+ {
+ struct mxc_gpio_port *port =
+ container_of(chip, struct mxc_gpio_port, chip);
++ unsigned long flags;
+ u32 l;
+
++ spin_lock_irqsave(&port->lock, flags);
+ l = __raw_readl(port->base + GPIO_GDIR);
+ if (dir)
+ l |= 1 << offset;
+ else
+ l &= ~(1 << offset);
+ __raw_writel(l, port->base + GPIO_GDIR);
++ spin_unlock_irqrestore(&port->lock, flags);
+ }
+
+ static void mxc_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
+@@ -224,10 +236,13 @@ static void mxc_gpio_set(struct gpio_chip *chip,
unsigned offset, int value)
+ struct mxc_gpio_port *port =
+ container_of(chip, struct mxc_gpio_port, chip);
+ void __iomem *reg = port->base + GPIO_DR;
++ unsigned long flags;
+ u32 l;
+
++ spin_lock_irqsave(&port->lock, flags);
+ l = (__raw_readl(reg) & (~(1 << offset))) | (value << offset);
+ __raw_writel(l, reg);
++ spin_unlock_irqrestore(&port->lock, flags);
+ }
+
+ static int mxc_gpio_get(struct gpio_chip *chip, unsigned offset)
+@@ -269,7 +284,11 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int
cnt)
for (j = port[i].virtual_irq_start;
j < port[i].virtual_irq_start + 32; j++) {
set_irq_chip(j, &gpio_irq_chip);
@@ -6785,6 +6924,14 @@ index 7506d96..4f712db 100644
set_irq_flags(j, IRQF_VALID);
}
+@@ -280,6 +299,7 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int
cnt)
+ port[i].chip.set = mxc_gpio_set;
+ port[i].chip.base = i * 32;
+ port[i].chip.ngpio = 32;
++ spin_lock_init(&port[i].lock);
+
+ /* its a serious configuration bug when it fails */
+ BUG_ON( gpiochip_add(&port[i].chip) < 0 );
diff --git a/arch/arm/plat-mxc/include/mach/common.h
b/arch/arm/plat-mxc/include/mach/common.h
index 02c3cd0..bf23383 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
@@ -6798,6 +6945,18 @@ index 02c3cd0..bf23383 100644
+#endif
+
#endif
+diff --git a/arch/arm/plat-mxc/include/mach/gpio.h
b/arch/arm/plat-mxc/include/mach/gpio.h
+index 894d2f8..8e7d72d 100644
+--- a/arch/arm/plat-mxc/include/mach/gpio.h
++++ b/arch/arm/plat-mxc/include/mach/gpio.h
+@@ -36,6 +36,7 @@ struct mxc_gpio_port {
+ int virtual_irq_start;
+ struct gpio_chip chip;
+ u32 both_edges;
++ ipipe_spinlock_t lock;
+ };
+
+ int mxc_gpio_init(struct mxc_gpio_port*, int);
diff --git a/arch/arm/plat-mxc/time.c b/arch/arm/plat-mxc/time.c
index 88fb3a5..c34206c 100644
--- a/arch/arm/plat-mxc/time.c
@@ -7053,7 +7212,7 @@ index 7f50b61..915409e 100644
/**
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
-index 9298bc0..6108aa1 100644
+index 9298bc0..28dcf42 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -20,6 +20,7 @@
@@ -7064,6 +7223,15 @@ index 9298bc0..6108aa1 100644
#include <linux/io.h>
#include <mach/hardware.h>
+@@ -181,7 +182,7 @@ struct gpio_bank {
+ u32 saved_risingdetect;
+ #endif
+ u32 level_mask;
+- spinlock_t lock;
++ ipipe_spinlock_t lock;
+ struct gpio_chip chip;
+ struct clk *dbck;
+ };
@@ -1200,7 +1201,7 @@ static void gpio_irq_handler(unsigned int irq, struct
irq_desc *desc)
if (!(isr & 1))
continue;
@@ -7088,7 +7256,7 @@ index 20f1054..42a0b8d 100644
u32 omap_dm_timer_modify_idlect_mask(u32 inputmask);
struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer);
diff --git a/arch/arm/plat-pxa/gpio.c b/arch/arm/plat-pxa/gpio.c
-index 98548c6..e732e45 100644
+index 98548c6..54f8f57 100644
--- a/arch/arm/plat-pxa/gpio.c
+++ b/arch/arm/plat-pxa/gpio.c
@@ -17,6 +17,7 @@
@@ -7099,6 +7267,15 @@ index 98548c6..e732e45 100644
#include <mach/gpio.h>
+@@ -39,7 +40,7 @@ struct pxa_gpio_chip {
+ #endif
+ };
+
+-static DEFINE_SPINLOCK(gpio_lock);
++static IPIPE_DEFINE_SPINLOCK(gpio_lock);
+ static struct pxa_gpio_chip *pxa_gpio_chips;
+
+ #define for_each_gpio_chip(i, c) \
@@ -220,7 +221,7 @@ static void pxa_gpio_demux_handler(unsigned int irq,
struct irq_desc *desc)
while (n < BITS_PER_LONG) {
loop = 1;
@@ -7117,6 +7294,72 @@ index 98548c6..e732e45 100644
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
+diff --git a/arch/arm/plat-s3c/gpio.c b/arch/arm/plat-s3c/gpio.c
+index 260fdc6..f5a203a 100644
+--- a/arch/arm/plat-s3c/gpio.c
++++ b/arch/arm/plat-s3c/gpio.c
+@@ -39,7 +39,7 @@ static __init void s3c_gpiolib_track(struct s3c_gpio_chip
*chip)
+ * chip is as following:
+ *
+ * base + 0x00: Control register, 2 bits per gpio
+- * gpio n: 2 bits starting at (2*n)
++ * gpio n: 2 bits starting at (2*n)
+ * 00 = input, 01 = output, others mean special-function
+ * base + 0x04: Data register, 1 bit per gpio
+ * bit n: data bit n
+@@ -52,14 +52,14 @@ static int s3c_gpiolib_input(struct gpio_chip *chip,
unsigned offset)
+ unsigned long flags;
+ unsigned long con;
+
+- local_irq_save(flags);
++ local_irq_save_hw(flags);
+
+ con = __raw_readl(base + 0x00);
+ con &= ~(3 << (offset * 2));
+
+ __raw_writel(con, base + 0x00);
+
+- local_irq_restore(flags);
++ local_irq_restore_hw(flags);
+ return 0;
+ }
+
+@@ -72,7 +72,7 @@ static int s3c_gpiolib_output(struct gpio_chip *chip,
+ unsigned long dat;
+ unsigned long con;
+
+- local_irq_save(flags);
++ local_irq_save_hw(flags);
+
+ dat = __raw_readl(base + 0x04);
+ dat &= ~(1 << offset);
+@@ -87,7 +87,7 @@ static int s3c_gpiolib_output(struct gpio_chip *chip,
+ __raw_writel(con, base + 0x00);
+ __raw_writel(dat, base + 0x04);
+
+- local_irq_restore(flags);
++ local_irq_restore_hw(flags);
+ return 0;
+ }
+
+@@ -99,7 +99,7 @@ static void s3c_gpiolib_set(struct gpio_chip *chip,
+ unsigned long flags;
+ unsigned long dat;
+
+- local_irq_save(flags);
++ local_irq_save_hw(flags);
+
+ dat = __raw_readl(base + 0x04);
+ dat &= ~(1 << offset);
+@@ -107,7 +107,7 @@ static void s3c_gpiolib_set(struct gpio_chip *chip,
+ dat |= 1 << offset;
+ __raw_writel(dat, base + 0x04);
+
+- local_irq_restore(flags);
++ local_irq_restore_hw(flags);
+ }
+
+ static int s3c_gpiolib_get(struct gpio_chip *chip, unsigned offset)
diff --git a/arch/arm/plat-s3c/time.c b/arch/arm/plat-s3c/time.c
index 3b27b29..976fe03 100644
--- a/arch/arm/plat-s3c/time.c
@@ -7769,41 +8012,19 @@ index 2d7423a..c0c7b4b 100644
preempt_enable();
}
-diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
-index 827da08..8f59245 100644
---- a/drivers/i2c/busses/i2c-omap.c
-+++ b/drivers/i2c/busses/i2c-omap.c
-@@ -449,6 +449,10 @@ static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
- if (msg->len == 0)
- return -EINVAL;
-
-+#ifdef CONFIG_IPIPE
-+ disable_irq(dev->irq);
-+#endif /* CONFIG_IPIPE */
-+
- omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
-
- /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
-@@ -492,6 +496,9 @@ static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
-
- /* Let the user know if i2c is in a bad state */
- if (time_after(jiffies, delay)) {
-+#ifdef CONFIG_IPIPE
-+ enable_irq(dev->irq);
-+#endif /* CONFIG_IPIPE */
- dev_err(dev->dev, "controller timed out "
- "waiting for start condition to finish\n");
- return -ETIMEDOUT;
-@@ -503,6 +510,9 @@ static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
- w &= ~OMAP_I2C_CON_STT;
- omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
- }
-+#ifdef CONFIG_IPIPE
-+ enable_irq(dev->irq);
-+#endif /* CONFIG_IPIPE */
-
- /*
- * REVISIT: We should abort the transfer on signals, but the bus goes
+diff --git a/drivers/mfd/twl4030-irq.c b/drivers/mfd/twl4030-irq.c
+index 7d43083..2dc8724 100644
+--- a/drivers/mfd/twl4030-irq.c
++++ b/drivers/mfd/twl4030-irq.c
+@@ -230,7 +230,7 @@ static int twl4030_irq_thread(void *data)
+ note_interrupt(module_irq, d,
+ IRQ_NONE);
+ else
+- d->handle_irq(module_irq, d);
++ ipipe_handle_irq_cond(module_irq);
+ }
+ }
+ local_irq_enable();
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 68ab39d..ede141b 100644
--- a/drivers/misc/Kconfig
diff --git a/ksrc/arch/arm/patches/adeos-ipipe-2.6.33-arm-1.17-01.patch
b/ksrc/arch/arm/patches/adeos-ipipe-2.6.33-arm-1.17-02.patch
similarity index 98%
rename from ksrc/arch/arm/patches/adeos-ipipe-2.6.33-arm-1.17-01.patch
rename to ksrc/arch/arm/patches/adeos-ipipe-2.6.33-arm-1.17-02.patch
index 22f5d3f..21310af 100644
--- a/ksrc/arch/arm/patches/adeos-ipipe-2.6.33-arm-1.17-01.patch
+++ b/ksrc/arch/arm/patches/adeos-ipipe-2.6.33-arm-1.17-02.patch
@@ -630,7 +630,7 @@ index 0000000..cfdf14a
+#endif /* __ASM_ARM_FCSE_H */
diff --git a/arch/arm/include/asm/ipipe.h b/arch/arm/include/asm/ipipe.h
new file mode 100644
-index 0000000..f8880e0
+index 0000000..98d3f47
--- /dev/null
+++ b/arch/arm/include/asm/ipipe.h
@@ -0,0 +1,274 @@
@@ -665,10 +665,10 @@ index 0000000..f8880e0
+#include <linux/ipipe_percpu.h>
+#include <mach/irqs.h> /* For __IPIPE_FEATURE_PIC_MUTE */
+
-+#define IPIPE_ARCH_STRING "1.17-01"
++#define IPIPE_ARCH_STRING "1.17-02"
+#define IPIPE_MAJOR_NUMBER 1
+#define IPIPE_MINOR_NUMBER 17
-+#define IPIPE_PATCH_NUMBER 1
++#define IPIPE_PATCH_NUMBER 2
+
+#ifdef CONFIG_SMP
+#error "I-pipe/arm: SMP not yet implemented"
@@ -5008,6 +5008,61 @@ index 3bbf40f..cfb1f44 100644
+EXPORT_SYMBOL(__ipipe_mach_release_timer);
+
+#endif /* CONFIG_IPIPE */
+diff --git a/arch/arm/mach-ixp4xx/include/mach/platform.h
b/arch/arm/mach-ixp4xx/include/mach/platform.h
+index e824c02..126b297 100644
+--- a/arch/arm/mach-ixp4xx/include/mach/platform.h
++++ b/arch/arm/mach-ixp4xx/include/mach/platform.h
+@@ -72,8 +72,8 @@ extern unsigned long ixp4xx_exp_bus_size;
+ /*
+ * Clock Speed Definitions.
+ */
+-#define IXP4XX_PERIPHERAL_BUS_CLOCK (66) /* 66Mhzi APB BUS */
+-#define IXP4XX_UART_XTAL 14745600
++#define IXP4XX_PERIPHERAL_BUS_CLOCK (66) /* 66Mhzi APB BUS */
++#define IXP4XX_UART_XTAL 14745600
+
+ /*
+ * This structure provide a means for the board setup code
+@@ -138,7 +138,7 @@ extern struct pci_bus *ixp4xx_scan_bus(int nr, struct
pci_sys_data *sys);
+ */
+ /* GPIO pin types */
+ #define IXP4XX_GPIO_OUT 0x1
+-#define IXP4XX_GPIO_IN 0x2
++#define IXP4XX_GPIO_IN 0x2
+
+ /* GPIO signal types */
+ #define IXP4XX_GPIO_LOW 0
+@@ -150,10 +150,14 @@ extern struct pci_bus *ixp4xx_scan_bus(int nr, struct
pci_sys_data *sys);
+
+ static inline void gpio_line_config(u8 line, u32 direction)
+ {
++ unsigned long flags;
++
++ local_irq_save_hw(flags);
+ if (direction == IXP4XX_GPIO_IN)
+ *IXP4XX_GPIO_GPOER |= (1 << line);
+ else
+ *IXP4XX_GPIO_GPOER &= ~(1 << line);
++ local_irq_restore_hw(flags);
+ }
+
+ static inline void gpio_line_get(u8 line, int *value)
+@@ -163,11 +167,14 @@ static inline void gpio_line_get(u8 line, int *value)
+
+ static inline void gpio_line_set(u8 line, int value)
+ {
++ unsigned long flags;
++
++ local_irq_save_hw(flags);
+ if (value == IXP4XX_GPIO_HIGH)
+ *IXP4XX_GPIO_GPOUTR |= (1 << line);
+ else if (value == IXP4XX_GPIO_LOW)
+ *IXP4XX_GPIO_GPOUTR &= ~(1 << line);
++ local_irq_restore_hw(flags);
+ }
+
+ #endif // __ASSEMBLY__
+-
diff --git a/arch/arm/mach-mx25/devices.c b/arch/arm/mach-mx25/devices.c
index 9fdeea1..89f74e8 100644
--- a/arch/arm/mach-mx25/devices.c
@@ -5806,6 +5861,35 @@ index 0c049b9..23a5c90 100644
}
}
}
+diff --git a/arch/arm/mach-sa1100/gpio.c b/arch/arm/mach-sa1100/gpio.c
+index 0d3829a..873f883 100644
+--- a/arch/arm/mach-sa1100/gpio.c
++++ b/arch/arm/mach-sa1100/gpio.c
+@@ -32,9 +32,9 @@ static int sa1100_direction_input(struct gpio_chip *chip,
unsigned offset)
+ {
+ unsigned long flags;
+
+- local_irq_save(flags);
++ local_irq_save_hw(flags);
+ GPDR &= ~GPIO_GPIO(offset);
+- local_irq_restore(flags);
++ local_irq_restore_hw(flags);
+ return 0;
+ }
+
+@@ -42,10 +42,10 @@ static int sa1100_direction_output(struct gpio_chip *chip,
unsigned offset, int
+ {
+ unsigned long flags;
+
+- local_irq_save(flags);
++ local_irq_save_hw(flags);
+ sa1100_gpio_set(chip, offset, value);
+ GPDR |= GPIO_GPIO(offset);
+- local_irq_restore(flags);
++ local_irq_restore_hw(flags);
+ return 0;
+ }
+
diff --git a/arch/arm/mach-sa1100/irq.c b/arch/arm/mach-sa1100/irq.c
index 3093d46..04a56d2 100644
--- a/arch/arm/mach-sa1100/irq.c
@@ -6837,7 +6921,7 @@ index 386e0d5..0bb140e 100644
+}
+#endif /* CONFIG_IPIPE */
diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c
-index d65ebe3..2eedd79 100644
+index d65ebe3..6c65f39 100644
--- a/arch/arm/plat-mxc/gpio.c
+++ b/arch/arm/plat-mxc/gpio.c
@@ -23,6 +23,7 @@
@@ -6848,7 +6932,29 @@ index d65ebe3..2eedd79 100644
#include <mach/hardware.h>
#include <asm-generic/bug.h>
-@@ -174,8 +175,7 @@ static void mxc_gpio_irq_handler(struct mxc_gpio_port
*port, u32 irq_stat)
+@@ -87,6 +88,7 @@ static int gpio_set_irq_type(u32 irq, u32 type)
+ {
+ u32 gpio = irq_to_gpio(irq);
+ struct mxc_gpio_port *port = &mxc_gpio_ports[gpio / 32];
++ unsigned long flags;
+ u32 bit, val;
+ int edge;
+ void __iomem *reg = port->base;
+@@ -120,11 +122,13 @@ static int gpio_set_irq_type(u32 irq, u32 type)
+ return -EINVAL;
+ }
+
++ spin_lock_irqsave(&port->lock, flags);
+ reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
+ bit = gpio & 0xf;
+ val = __raw_readl(reg) & ~(0x3 << (bit << 1));
+ __raw_writel(val | (edge << (bit << 1)), reg);
+ _clear_gpio_irqstatus(port, gpio & 0x1f);
++ spin_unlock_irqrestore(&port->lock, flags);
+
+ return 0;
+ }
+@@ -174,8 +178,7 @@ static void mxc_gpio_irq_handler(struct mxc_gpio_port
*port, u32 irq_stat)
if (port->both_edges & (1 << (gpio & 31)))
mxc_flip_edge(port, gpio);
@@ -6858,6 +6964,46 @@ index d65ebe3..2eedd79 100644
}
}
+@@ -222,14 +225,17 @@ static void _set_gpio_direction(struct gpio_chip *chip,
unsigned offset,
+ {
+ struct mxc_gpio_port *port =
+ container_of(chip, struct mxc_gpio_port, chip);
++ unsigned long flags;
+ u32 l;
+
++ spin_lock_irqsave(&port->lock, flags);
+ l = __raw_readl(port->base + GPIO_GDIR);
+ if (dir)
+ l |= 1 << offset;
+ else
+ l &= ~(1 << offset);
+ __raw_writel(l, port->base + GPIO_GDIR);
++ spin_unlock_irqrestore(&port->lock, flags);
+ }
+
+ static void mxc_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
+@@ -237,10 +243,13 @@ static void mxc_gpio_set(struct gpio_chip *chip,
unsigned offset, int value)
+ struct mxc_gpio_port *port =
+ container_of(chip, struct mxc_gpio_port, chip);
+ void __iomem *reg = port->base + GPIO_DR;
++ unsigned long flags;
+ u32 l;
+
++ spin_lock_irqsave(&port->lock, flags);
+ l = (__raw_readl(reg) & (~(1 << offset))) | (value << offset);
+ __raw_writel(l, reg);
++ spin_unlock_irqrestore(&port->lock, flags);
+ }
+
+ static int mxc_gpio_get(struct gpio_chip *chip, unsigned offset)
+@@ -293,6 +302,7 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int
cnt)
+ port[i].chip.set = mxc_gpio_set;
+ port[i].chip.base = i * 32;
+ port[i].chip.ngpio = 32;
++ spin_lock_init(&port[i].lock);
+
+ /* its a serious configuration bug when it fails */
+ BUG_ON( gpiochip_add(&port[i].chip) < 0 );
diff --git a/arch/arm/plat-mxc/include/mach/common.h
b/arch/arm/plat-mxc/include/mach/common.h
index 4bf1068..1cf801f 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
@@ -6871,6 +7017,18 @@ index 4bf1068..1cf801f 100644
+#endif
+
#endif
+diff --git a/arch/arm/plat-mxc/include/mach/gpio.h
b/arch/arm/plat-mxc/include/mach/gpio.h
+index 894d2f8..8e7d72d 100644
+--- a/arch/arm/plat-mxc/include/mach/gpio.h
++++ b/arch/arm/plat-mxc/include/mach/gpio.h
+@@ -36,6 +36,7 @@ struct mxc_gpio_port {
+ int virtual_irq_start;
+ struct gpio_chip chip;
+ u32 both_edges;
++ ipipe_spinlock_t lock;
+ };
+
+ int mxc_gpio_init(struct mxc_gpio_port*, int);
diff --git a/arch/arm/plat-mxc/time.c b/arch/arm/plat-mxc/time.c
index 844567e..bc60cac 100644
--- a/arch/arm/plat-mxc/time.c
@@ -7134,7 +7292,7 @@ index 08ccf89..4d1abd7 100644
/**
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
-index d2422c7..589a4bb 100644
+index d2422c7..f1d85ff 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -20,7 +20,9 @@
@@ -7147,6 +7305,15 @@ index d2422c7..589a4bb 100644
#include <mach/hardware.h>
#include <asm/irq.h>
+@@ -193,7 +195,7 @@ struct gpio_bank {
+ #endif
+ u32 level_mask;
+ u32 toggle_mask;
+- spinlock_t lock;
++ ipipe_spinlock_t lock;
+ struct gpio_chip chip;
+ struct clk *dbck;
+ u32 mod_usage;
@@ -1345,8 +1347,7 @@ static void gpio_irq_handler(unsigned int irq, struct
irq_desc *desc)
if (bank->toggle_mask & (1 << gpio_index))
_toggle_gpio_edge_triggering(bank, gpio_index);
@@ -7172,7 +7339,7 @@ index 20f1054..42a0b8d 100644
u32 omap_dm_timer_modify_idlect_mask(u32 inputmask);
struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer);
diff --git a/arch/arm/plat-pxa/gpio.c b/arch/arm/plat-pxa/gpio.c
-index 98548c6..e732e45 100644
+index 98548c6..54f8f57 100644
--- a/arch/arm/plat-pxa/gpio.c
+++ b/arch/arm/plat-pxa/gpio.c
@@ -17,6 +17,7 @@
@@ -7183,6 +7350,15 @@ index 98548c6..e732e45 100644
#include <mach/gpio.h>
+@@ -39,7 +40,7 @@ struct pxa_gpio_chip {
+ #endif
+ };
+
+-static DEFINE_SPINLOCK(gpio_lock);
++static IPIPE_DEFINE_SPINLOCK(gpio_lock);
+ static struct pxa_gpio_chip *pxa_gpio_chips;
+
+ #define for_each_gpio_chip(i, c) \
@@ -220,7 +221,7 @@ static void pxa_gpio_demux_handler(unsigned int irq,
struct irq_desc *desc)
while (n < BITS_PER_LONG) {
loop = 1;
@@ -7201,6 +7377,72 @@ index 98548c6..e732e45 100644
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
+diff --git a/arch/arm/plat-s3c/gpio.c b/arch/arm/plat-s3c/gpio.c
+index 5ff24e0..03e6c09 100644
+--- a/arch/arm/plat-s3c/gpio.c
++++ b/arch/arm/plat-s3c/gpio.c
+@@ -39,7 +39,7 @@ static __init void s3c_gpiolib_track(struct s3c_gpio_chip
*chip)
+ * chip is as following:
+ *
+ * base + 0x00: Control register, 2 bits per gpio
+- * gpio n: 2 bits starting at (2*n)
++ * gpio n: 2 bits starting at (2*n)
+ * 00 = input, 01 = output, others mean special-function
+ * base + 0x04: Data register, 1 bit per gpio
+ * bit n: data bit n
+@@ -52,14 +52,14 @@ static int s3c_gpiolib_input(struct gpio_chip *chip,
unsigned offset)
+ unsigned long flags;
+ unsigned long con;
+
+- local_irq_save(flags);
++ local_irq_save_hw(flags);
+
+ con = __raw_readl(base + 0x00);
+ con &= ~(3 << (offset * 2));
+
+ __raw_writel(con, base + 0x00);
+
+- local_irq_restore(flags);
++ local_irq_restore_hw(flags);
+ return 0;
+ }
+
+@@ -72,7 +72,7 @@ static int s3c_gpiolib_output(struct gpio_chip *chip,
+ unsigned long dat;
+ unsigned long con;
+
+- local_irq_save(flags);
++ local_irq_save_hw(flags);
+
+ dat = __raw_readl(base + 0x04);
+ dat &= ~(1 << offset);
+@@ -87,7 +87,7 @@ static int s3c_gpiolib_output(struct gpio_chip *chip,
+ __raw_writel(con, base + 0x00);
+ __raw_writel(dat, base + 0x04);
+
+- local_irq_restore(flags);
++ local_irq_restore_hw(flags);
+ return 0;
+ }
+
+@@ -99,7 +99,7 @@ static void s3c_gpiolib_set(struct gpio_chip *chip,
+ unsigned long flags;
+ unsigned long dat;
+
+- local_irq_save(flags);
++ local_irq_save_hw(flags);
+
+ dat = __raw_readl(base + 0x04);
+ dat &= ~(1 << offset);
+@@ -107,7 +107,7 @@ static void s3c_gpiolib_set(struct gpio_chip *chip,
+ dat |= 1 << offset;
+ __raw_writel(dat, base + 0x04);
+
+- local_irq_restore(flags);
++ local_irq_restore_hw(flags);
+ }
+
+ static int s3c_gpiolib_get(struct gpio_chip *chip, unsigned offset)
diff --git a/arch/arm/plat-s3c/time.c b/arch/arm/plat-s3c/time.c
index 3b27b29..976fe03 100644
--- a/arch/arm/plat-s3c/time.c
@@ -7879,41 +8121,19 @@ index a63c4be..1fdff52 100644
preempt_enable();
}
-diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
-index 0037e31..8d608a1 100644
---- a/drivers/i2c/busses/i2c-omap.c
-+++ b/drivers/i2c/busses/i2c-omap.c
-@@ -478,6 +478,10 @@ static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
- if (msg->len == 0)
- return -EINVAL;
-
-+#ifdef CONFIG_IPIPE
-+ disable_irq(dev->irq);
-+#endif /* CONFIG_IPIPE */
-+
- omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
-
- /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
-@@ -521,6 +525,9 @@ static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
-
- /* Let the user know if i2c is in a bad state */
- if (time_after(jiffies, delay)) {
-+#ifdef CONFIG_IPIPE
-+ enable_irq(dev->irq);
-+#endif /* CONFIG_IPIPE */
- dev_err(dev->dev, "controller timed out "
- "waiting for start condition to finish\n");
- return -ETIMEDOUT;
-@@ -532,6 +539,9 @@ static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
- w &= ~OMAP_I2C_CON_STT;
- omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
- }
-+#ifdef CONFIG_IPIPE
-+ enable_irq(dev->irq);
-+#endif /* CONFIG_IPIPE */
-
- /*
- * REVISIT: We should abort the transfer on signals, but the bus goes
+diff --git a/drivers/mfd/twl4030-irq.c b/drivers/mfd/twl4030-irq.c
+index 9df9a5a..8b91420 100644
+--- a/drivers/mfd/twl4030-irq.c
++++ b/drivers/mfd/twl4030-irq.c
+@@ -332,7 +332,7 @@ static int twl4030_irq_thread(void *data)
+ note_interrupt(module_irq, d,
+ IRQ_NONE);
+ else
+- d->handle_irq(module_irq, d);
++ ipipe_handle_irq_cond(module_irq);
+ }
+ }
+ local_irq_enable();
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index e3551d2..d8f7317 100644
--- a/drivers/misc/Kconfig
@@ -10214,7 +10434,7 @@ index 328bca6..4ed869d 100644
#ifdef CONFIG_DEBUG_SPINLOCK_SLEEP
diff --git a/include/linux/lockdep.h b/include/linux/lockdep.h
-index 9ccf0e2..f500f1e 100644
+index 9ccf0e2..ec98e63 100644
--- a/include/linux/lockdep.h
+++ b/include/linux/lockdep.h
@@ -395,7 +395,7 @@ do {
\
@@ -10226,6 +10446,15 @@ index 9ccf0e2..f500f1e 100644
/*
* On lockdep we dont want the hand-coded irq-enable of
+@@ -403,7 +403,7 @@ do {
\
+ * that interrupts are not re-enabled during lock-acquire:
+ */
+ #define LOCK_CONTENDED_FLAGS(_lock, try, lock, lockfl, flags) \
+- LOCK_CONTENDED((_lock), (try), (lock))
++ LOCK_CONTENDED((_lock), (try), lock)
+
+ #else /* CONFIG_LOCKDEP */
+
diff --git a/include/linux/preempt.h b/include/linux/preempt.h
index 2e681d9..130b7d5 100644
--- a/include/linux/preempt.h
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