Module: xenomai-2.6
Branch: master
Commit: de0dabf48e2143f296660c098141b381dc923801
URL:    
http://git.xenomai.org/?p=xenomai-2.6.git;a=commit;h=de0dabf48e2143f296660c098141b381dc923801

Author: Charles Steinkuehler <char...@steinkuehler.net>
Date:   Tue Aug 27 20:45:12 2013 +0200

hal/arm: Add pre/post patch set for BeagleBone 3.8.13 kernel

Signed-off-by: Charles Steinkuehler <char...@steinkuehler.net>

---

 ksrc/arch/arm/patches/README                       |   12 +-
 .../ipipe-core-3.2.21-beaglebone-post.patch        |  286 ----------
 .../ipipe-core-3.2.21-beaglebone-pre.patch         |  555 --------------------
 .../ipipe-core-3.8.13-beaglebone-post.patch        |   16 +
 .../ipipe-core-3.8.13-beaglebone-pre.patch         |   16 +
 5 files changed, 38 insertions(+), 847 deletions(-)

diff --git a/ksrc/arch/arm/patches/README b/ksrc/arch/arm/patches/README
index 855a709..14211c2 100644
--- a/ksrc/arch/arm/patches/README
+++ b/ksrc/arch/arm/patches/README
@@ -59,11 +59,11 @@ o Texas Instrument OMAP3 and OMAP4
 
 ---- Beaglebone
 
-1- Checkout the 
"origin/linux-ti33x-psp-3.2.21-r13g+gitr720e07b4c1f687b61b147b31c698cb6816d72f01"
 branch in the Koen Kooi repository [3], or see [4] for an
-alternate repository,
-2- apply beaglebone/ipipe-core-3.2.21-beaglebone-pre.patch,
-3- apply ipipe-core-3.2.21-arm*.patch
-4- apply beaglebone/ipipe-core-3.2.21-beaglebone-post.patch,
+1- Checkout the "am33x-v3.8" branch in the Robert Nelson repository [3], 
+the patch has been tested with commit 3fc8a73d782231ab2750ff29793a760e8fa076bb
+2- apply beaglebone/ipipe-core-3.8.13-beaglebone-pre.patch
+3- apply ipipe-core-3.8.13-arm-1.patch
+4- apply beaglebone/ipipe-core-3.8.13-beaglebone-post.patch
 5- you can resume to generic installation instructions.
 
 
@@ -87,7 +87,7 @@ From [5]:
 
 [1] http://opensource.freescale.com/pub/scm/imx/linux-2.6-imx.git
 [2] git://git.denx.de/linux-denx.git
-[3] git://github.com/koenkooi/linux
+[3] https://github.com/RobertCNelson/linux-dev
 [4] http://www.xenomai.org/pipermail/xenomai/2013-February/027584.html
 [5] http://www.xenomai.org/pipermail/xenomai/2013-February/027752.html
 [6] git://github.com/Xilinx/linux-xlnx.git
diff --git 
a/ksrc/arch/arm/patches/beaglebone/ipipe-core-3.2.21-beaglebone-post.patch 
b/ksrc/arch/arm/patches/beaglebone/ipipe-core-3.2.21-beaglebone-post.patch
deleted file mode 100644
index 46eeba3..0000000
--- a/ksrc/arch/arm/patches/beaglebone/ipipe-core-3.2.21-beaglebone-post.patch
+++ /dev/null
@@ -1,286 +0,0 @@
---- a/arch/arm/mach-omap2/irq.c
-+++ b/arch/arm/mach-omap2/irq.c
-@@ -15,6 +15,7 @@
- #include <linux/interrupt.h>
- #include <linux/io.h>
- #include <mach/hardware.h>
-+#include <asm/exception.h>
- #include <asm/ipipe.h>
- #include <asm/mach/irq.h>
- 
-@@ -37,6 +38,11 @@
- /* Number of IRQ state bits in each MIR register */
- #define IRQ_BITS_PER_REG      32
- 
-+#define OMAP2_IRQ_BASE                OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE)
-+#define OMAP3_IRQ_BASE                OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE)
-+#define INTCPS_SIR_IRQ_OFFSET 0x0040  /* omap2/3 active interrupt offset */
-+#define ACTIVEIRQ_MASK                0x7f    /* omap2/3 active interrupt 
bits */
-+
- #if !defined(MULTI_OMAP1) && !defined(MULTI_OMAP2)
- #define inline_single inline
- #else
-@@ -52,10 +58,12 @@
- static struct omap_irq_bank {
-       void __iomem *base_reg;
-       unsigned int nr_irqs;
-+      unsigned int nr_regs_req;
- } __attribute__ ((aligned(4))) irq_banks[] = {
-       {
-               /* MPU INTC */
-               .nr_irqs        = 96,
-+              .nr_regs_req    = 3,
-       },
- };
- 
-@@ -65,8 +73,8 @@ struct omap3_intc_regs {
-       u32 protection;
-       u32 idle;
-       u32 threshold;
--      u32 ilr[INTCPS_NR_IRQS];
--      u32 mir[INTCPS_NR_MIR_REGS];
-+      u32 ilr[INTCPS_MAX_NR_IRQS];
-+      u32 mir[INTCPS_MAX_NR_REGS_REQ];
- };
- 
- /* INTC bank register get/set */
-@@ -162,6 +170,7 @@ omap_alloc_gc(void __iomem *base, unsign
- 
- static void __init omap_init_irq(u32 base, int nr_irqs)
- {
-+      void __iomem *omap_irq_base;
-       unsigned long nr_of_irqs = 0;
-       unsigned int nr_banks = 0;
-       int i, j;
-@@ -174,6 +183,7 @@ static void __init omap_init_irq(u32 bas
-               struct omap_irq_bank *bank = irq_banks + i;
- 
-               bank->nr_irqs = nr_irqs;
-+              bank->nr_regs_req = 0;
- 
-               /* Static mapping, never released */
-               bank->base_reg = ioremap(base, SZ_4K);
-@@ -184,8 +194,10 @@ static void __init omap_init_irq(u32 bas
- 
-               omap_irq_bank_init_one(bank);
- 
--              for (j = 0; j < bank->nr_irqs; j += 32)
-+              for (j = 0; j < bank->nr_irqs; j += 32) {
-                       omap_alloc_gc(bank->base_reg + j, j, 32);
-+                      bank->nr_regs_req++;
-+              }
- 
-               nr_of_irqs += bank->nr_irqs;
-               nr_banks++;
-@@ -205,6 +217,50 @@ void __init omap3_init_irq(void)
-       omap_init_irq(OMAP34XX_IC_BASE, 96);
- }
- 
-+void __init ti81xx_init_irq(void)
-+{
-+      omap_init_irq(OMAP34XX_IC_BASE, 128);
-+}
-+
-+static inline void omap_intc_handle_irq(void __iomem *base_addr,
-+              unsigned int no_regs_req, struct pt_regs *regs)
-+{
-+      u32 irqnr = 0;
-+
-+      do {
-+              int i = 0;
-+
-+              for (i = 0; i < no_regs_req; i++) {
-+                      irqnr = readl_relaxed(base_addr + 0x98 + (0x20 * i));
-+                      if (irqnr)
-+                              goto out;
-+              }
-+
-+out:
-+              if (!irqnr)
-+                      break;
-+
-+              irqnr = readl_relaxed(base_addr + INTCPS_SIR_IRQ_OFFSET);
-+              irqnr &= ACTIVEIRQ_MASK;
-+
-+              if (irqnr)
-+              {
-+#ifdef CONFIG_IPIPE
-+                      ipipe_handle_multi_irq(irqnr, regs);
-+#else
-+                      handle_IRQ(irqnr, regs);
-+#endif
-+              }
-+              
-+      } while (irqnr);
-+}
-+
-+asmlinkage void __exception_irq_entry omap2_intc_handle_irq(struct pt_regs 
*regs)
-+{
-+      void __iomem *base_addr = OMAP2_IRQ_BASE;
-+      omap_intc_handle_irq(base_addr, irq_banks[0].nr_regs_req, regs);
-+}
-+
- void __init ti816x_init_irq(void)
- {
-       omap_init_irq(OMAP34XX_IC_BASE, 128);
-@@ -292,10 +348,10 @@ void omap_intc_save_context(void)
-                       intc_bank_read_reg(bank, INTC_IDLE);
-               intc_context[ind].threshold =
-                       intc_bank_read_reg(bank, INTC_THRESHOLD);
--              for (i = 0; i < INTCPS_NR_IRQS; i++)
-+              for (i = 0; i < bank->nr_irqs; i++)
-                       intc_context[ind].ilr[i] =
-                               intc_bank_read_reg(bank, (0x100 + 0x4*i));
--              for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
-+              for (i = 0; i < bank->nr_regs_req; i++)
-                       intc_context[ind].mir[i] =
-                               intc_bank_read_reg(&irq_banks[0], INTC_MIR0 +
-                               (0x20 * i));
-@@ -318,10 +374,10 @@ void omap_intc_restore_context(void)
-                                       bank, INTC_IDLE);
-               intc_bank_write_reg(intc_context[ind].threshold,
-                                       bank, INTC_THRESHOLD);
--              for (i = 0; i < INTCPS_NR_IRQS; i++)
-+              for (i = 0; i < bank->nr_irqs; i++)
-                       intc_bank_write_reg(intc_context[ind].ilr[i],
-                               bank, (0x100 + 0x4*i));
--              for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
-+              for (i = 0; i < bank->nr_regs_req; i++)
-                       intc_bank_write_reg(intc_context[ind].mir[i],
-                                &irq_banks[0], INTC_MIR0 + (0x20 * i));
-       }
-@@ -348,4 +404,10 @@ void omap3_intc_resume_idle(void)
-       /* Re-enable autoidle */
-       intc_bank_write_reg(1, &irq_banks[0], INTC_SYSCONFIG);
- }
-+
-+asmlinkage void __exception_irq_entry omap3_intc_handle_irq(struct pt_regs 
*regs)
-+{
-+      void __iomem *base_addr = OMAP3_IRQ_BASE;
-+      omap_intc_handle_irq(base_addr, irq_banks[0].nr_regs_req, regs);
-+}
- #endif /* CONFIG_ARCH_OMAP3 */
---- a/arch/arm/mach-omap2/mux.c
-+++ b/arch/arm/mach-omap2/mux.c
-@@ -806,7 +806,8 @@ static void __init omap_mux_free_names(s
- static int __init omap_mux_late_init(void)
- {
-       struct omap_mux_partition *partition;
--      int ret;
-+      int ret = -1;
-+      int irq = -1;
- 
-       list_for_each_entry(partition, &mux_partitions, node) {
-               struct omap_mux_entry *e, *tmp;
-@@ -827,13 +828,18 @@ static int __init omap_mux_late_init(voi
-               }
-       }
- 
--      ret = request_irq(omap_prcm_event_to_irq("io"),
--              omap_hwmod_mux_handle_irq, IRQF_SHARED | IRQF_NO_SUSPEND,
--                      "hwmod_io", omap_mux_late_init);
--
-+      irq = omap_prcm_event_to_irq("io");
-+      
-+      if(irq >= 0)
-+      {
-+              ret = request_irq(irq,
-+                      omap_hwmod_mux_handle_irq, IRQF_SHARED | 
IRQF_NO_SUSPEND,
-+                              "hwmod_io", omap_mux_late_init);
-+      }
-+      
-       if (ret)
--              pr_warning("mux: Failed to setup hwmod io irq %d\n", ret);
--
-+              pr_warning("mux: Failed to setup hwmod io irq %d\n", irq);
-+      
-       omap_mux_dbg_init();
- 
-       return 0;
---- a/arch/arm/plat-omap/include/plat/irqs.h
-+++ b/arch/arm/plat-omap/include/plat/irqs.h
-@@ -30,6 +30,7 @@
- 
- /* All OMAP4 specific defines are moved to irqs-44xx.h */
- #include "irqs-44xx.h"
-+#include "irqs-33xx.h"
- 
- /*
-  * IRQ numbers for interrupt handler 1
-@@ -357,7 +358,7 @@
- #define INT_35XX_EMAC_C0_TX_PULSE_IRQ 69
- #define INT_35XX_EMAC_C0_MISC_PULSE_IRQ       70
- #define INT_35XX_USBOTG_IRQ           71
--#define INT_35XX_UART4                        84
-+#define INT_35XX_UART4_IRQ            84
- #define INT_35XX_CCDC_VD0_IRQ         88
- #define INT_35XX_CCDC_VD1_IRQ         92
- #define INT_35XX_CCDC_VD2_IRQ         93
-@@ -433,6 +434,12 @@
- 
- #define OMAP_IRQ_BIT(irq)     (1 << ((irq) % 32))
- 
-+/*
-+ * Max from AM33XX device
-+ */
-+#define INTCPS_MAX_NR_REGS_REQ        4
-+#define INTCPS_MAX_NR_IRQS    128
-+
- #define INTCPS_NR_MIR_REGS    3
- #define INTCPS_NR_IRQS                96
- 
---- a/arch/arm/mach-omap2/timer.c
-+++ b/arch/arm/mach-omap2/timer.c
-@@ -63,17 +63,20 @@
- #define OMAP2_32K_SOURCE      "func_32k_ck"
- #define OMAP3_32K_SOURCE      "omap_32k_fck"
- #define OMAP4_32K_SOURCE      "sys_32k_ck"
-+#define AM33XX_CLKEV_SOURCE OMAP4_MPU_SOURCE
- #define AM33XX_RTC32K_SOURCE  "clk_32768_ck"
- 
- #ifdef CONFIG_OMAP_32K_TIMER
- #define OMAP2_CLKEV_SOURCE    OMAP2_32K_SOURCE
- #define OMAP3_CLKEV_SOURCE    OMAP3_32K_SOURCE
- #define OMAP4_CLKEV_SOURCE    OMAP4_32K_SOURCE
-+#define AM33XX_MPU_SOURCE     AM33XX_RTC32K_SOURCE
- #define OMAP3_SECURE_TIMER    12
- #else
- #define OMAP2_CLKEV_SOURCE    OMAP2_MPU_SOURCE
- #define OMAP3_CLKEV_SOURCE    OMAP3_MPU_SOURCE
- #define OMAP4_CLKEV_SOURCE    OMAP4_MPU_SOURCE
-+#define AM33XX_MPU_SOURCE     OMAP4_MPU_SOURCE
- #define OMAP3_SECURE_TIMER    1
- #endif
- 
-@@ -475,7 +478,15 @@ OMAP_SYS_TIMER_INIT(2, 1, OMAP2_CLKEV_SO
- OMAP_SYS_TIMER(2)
- #endif
- 
-+#ifdef CONFIG_ARCH_OMAP2
-+OMAP_SYS_TIMER_INIT(2, 1, OMAP2_CLKEV_SOURCE, 2, OMAP2_MPU_SOURCE)
-+OMAP_SYS_TIMER(2)
-+#endif
-+
- #ifdef CONFIG_ARCH_OMAP3
-+
-+#ifndef CONFIG_SOC_OMAPAM33XX
-+
- #ifndef CONFIG_IPIPE
- OMAP_SYS_TIMER_INIT(3, 1, OMAP3_CLKEV_SOURCE, 2, OMAP3_MPU_SOURCE)
- #else
-@@ -485,8 +496,14 @@ OMAP_SYS_TIMER(3)
- OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE,
-                       2, OMAP3_MPU_SOURCE)
- OMAP_SYS_TIMER(3_secure)
--OMAP_SYS_TIMER_INIT(3_am33xx, 2, OMAP4_MPU_SOURCE, 1, AM33XX_RTC32K_SOURCE)
-+
-+#else // #ifdef CONFIG_SOC_OMAPAM33XX
-+
-+OMAP_SYS_TIMER_INIT(3_am33xx, 2, AM33XX_CLKEV_SOURCE, 1, AM33XX_MPU_SOURCE)
- OMAP_SYS_TIMER(3_am33xx)
-+
-+#endif
-+
- #endif
- 
- #ifdef CONFIG_ARCH_OMAP4
diff --git 
a/ksrc/arch/arm/patches/beaglebone/ipipe-core-3.2.21-beaglebone-pre.patch 
b/ksrc/arch/arm/patches/beaglebone/ipipe-core-3.2.21-beaglebone-pre.patch
deleted file mode 100644
index 09de6bf..0000000
--- a/ksrc/arch/arm/patches/beaglebone/ipipe-core-3.2.21-beaglebone-pre.patch
+++ /dev/null
@@ -1,555 +0,0 @@
---- a/arch/arm/common/gic.c
-+++ b/arch/arm/common/gic.c
-@@ -40,37 +40,14 @@
- #include <linux/slab.h>
- 
- #include <asm/irq.h>
--#include <asm/exception.h>
- #include <asm/mach/irq.h>
- #include <asm/hardware/gic.h>
- 
--union gic_base {
--      void __iomem *common_base;
--      void __percpu __iomem **percpu_base;
--};
--
--struct gic_chip_data {
--      unsigned int irq_offset;
--      union gic_base dist_base;
--      union gic_base cpu_base;
--#ifdef CONFIG_CPU_PM
--      u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)];
--      u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)];
--      u32 saved_spi_target[DIV_ROUND_UP(1020, 4)];
--      u32 __percpu *saved_ppi_enable;
--      u32 __percpu *saved_ppi_conf;
--#endif
--#ifdef CONFIG_IRQ_DOMAIN
--      struct irq_domain domain;
--#endif
--      unsigned int gic_irqs;
--#ifdef CONFIG_GIC_NON_BANKED
--      void __iomem *(*get_base)(union gic_base *);
--#endif
--};
--
- static DEFINE_RAW_SPINLOCK(irq_controller_lock);
- 
-+/* Address of GIC 0 CPU interface */
-+void __iomem *gic_cpu_base_addr __read_mostly;
-+
- /*
-  * Supported arch specific GIC irq extension.
-  * Default make them NULL.
-@@ -90,48 +67,16 @@ struct irq_chip gic_arch_extn = {
- 
- static struct gic_chip_data gic_data[MAX_GIC_NR] __read_mostly;
- 
--#ifdef CONFIG_GIC_NON_BANKED
--static void __iomem *gic_get_percpu_base(union gic_base *base)
--{
--      return *__this_cpu_ptr(base->percpu_base);
--}
--
--static void __iomem *gic_get_common_base(union gic_base *base)
--{
--      return base->common_base;
--}
--
--static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data)
--{
--      return data->get_base(&data->dist_base);
--}
--
--static inline void __iomem *gic_data_cpu_base(struct gic_chip_data *data)
--{
--      return data->get_base(&data->cpu_base);
--}
--
--static inline void gic_set_base_accessor(struct gic_chip_data *data,
--                                       void __iomem *(*f)(union gic_base *))
--{
--      data->get_base = f;
--}
--#else
--#define gic_data_dist_base(d) ((d)->dist_base.common_base)
--#define gic_data_cpu_base(d)  ((d)->cpu_base.common_base)
--#define gic_set_base_accessor(d,f)
--#endif
--
- static inline void __iomem *gic_dist_base(struct irq_data *d)
- {
-       struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
--      return gic_data_dist_base(gic_data);
-+      return gic_data->dist_base;
- }
- 
- static inline void __iomem *gic_cpu_base(struct irq_data *d)
- {
-       struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
--      return gic_data_cpu_base(gic_data);
-+      return gic_data->cpu_base;
- }
- 
- static inline unsigned int gic_irq(struct irq_data *d)
-@@ -270,32 +215,6 @@ static int gic_set_wake(struct irq_data
- #define gic_set_wake  NULL
- #endif
- 
--asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
--{
--      u32 irqstat, irqnr;
--      struct gic_chip_data *gic = &gic_data[0];
--      void __iomem *cpu_base = gic_data_cpu_base(gic);
--
--      do {
--              irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK);
--              irqnr = irqstat & ~0x1c00;
--
--              if (likely(irqnr > 15 && irqnr < 1021)) {
--                      irqnr = irq_domain_to_irq(&gic->domain, irqnr);
--                      handle_IRQ(irqnr, regs);
--                      continue;
--              }
--              if (irqnr < 16) {
--                      writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
--#ifdef CONFIG_SMP
--                      handle_IPI(irqnr, regs);
--#endif
--                      continue;
--              }
--              break;
--      } while (1);
--}
--
- static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
- {
-       struct gic_chip_data *chip_data = irq_get_handler_data(irq);
-@@ -306,7 +225,7 @@ static void gic_handle_cascade_irq(unsig
-       chained_irq_enter(chip, desc);
- 
-       raw_spin_lock(&irq_controller_lock);
--      status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK);
-+      status = readl_relaxed(chip_data->cpu_base + GIC_CPU_INTACK);
-       raw_spin_unlock(&irq_controller_lock);
- 
-       gic_irq = (status & 0x3ff);
-@@ -351,7 +270,7 @@ static void __init gic_dist_init(struct
-       u32 cpumask;
-       unsigned int gic_irqs = gic->gic_irqs;
-       struct irq_domain *domain = &gic->domain;
--      void __iomem *base = gic_data_dist_base(gic);
-+      void __iomem *base = gic->dist_base;
-       u32 cpu = 0;
- 
- #ifdef CONFIG_SMP
-@@ -411,8 +330,8 @@ static void __init gic_dist_init(struct
- 
- static void __cpuinit gic_cpu_init(struct gic_chip_data *gic)
- {
--      void __iomem *dist_base = gic_data_dist_base(gic);
--      void __iomem *base = gic_data_cpu_base(gic);
-+      void __iomem *dist_base = gic->dist_base;
-+      void __iomem *base = gic->cpu_base;
-       int i;
- 
-       /*
-@@ -449,7 +368,7 @@ static void gic_dist_save(unsigned int g
-               BUG();
- 
-       gic_irqs = gic_data[gic_nr].gic_irqs;
--      dist_base = gic_data_dist_base(&gic_data[gic_nr]);
-+      dist_base = gic_data[gic_nr].dist_base;
- 
-       if (!dist_base)
-               return;
-@@ -484,7 +403,7 @@ static void gic_dist_restore(unsigned in
-               BUG();
- 
-       gic_irqs = gic_data[gic_nr].gic_irqs;
--      dist_base = gic_data_dist_base(&gic_data[gic_nr]);
-+      dist_base = gic_data[gic_nr].dist_base;
- 
-       if (!dist_base)
-               return;
-@@ -520,8 +439,8 @@ static void gic_cpu_save(unsigned int gi
-       if (gic_nr >= MAX_GIC_NR)
-               BUG();
- 
--      dist_base = gic_data_dist_base(&gic_data[gic_nr]);
--      cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
-+      dist_base = gic_data[gic_nr].dist_base;
-+      cpu_base = gic_data[gic_nr].cpu_base;
- 
-       if (!dist_base || !cpu_base)
-               return;
-@@ -546,8 +465,8 @@ static void gic_cpu_restore(unsigned int
-       if (gic_nr >= MAX_GIC_NR)
-               BUG();
- 
--      dist_base = gic_data_dist_base(&gic_data[gic_nr]);
--      cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
-+      dist_base = gic_data[gic_nr].dist_base;
-+      cpu_base = gic_data[gic_nr].cpu_base;
- 
-       if (!dist_base || !cpu_base)
-               return;
-@@ -572,11 +491,6 @@ static int gic_notifier(struct notifier_
-       int i;
- 
-       for (i = 0; i < MAX_GIC_NR; i++) {
--#ifdef CONFIG_GIC_NON_BANKED
--              /* Skip over unused GICs */
--              if (!gic_data[i].get_base)
--                      continue;
--#endif
-               switch (cmd) {
-               case CPU_PM_ENTER:
-                       gic_cpu_save(i);
-@@ -650,9 +564,8 @@ const struct irq_domain_ops gic_irq_doma
- #endif
- };
- 
--void __init gic_init_bases(unsigned int gic_nr, int irq_start,
--                         void __iomem *dist_base, void __iomem *cpu_base,
--                         u32 percpu_offset)
-+void __init gic_init(unsigned int gic_nr, int irq_start,
-+      void __iomem *dist_base, void __iomem *cpu_base)
- {
-       struct gic_chip_data *gic;
-       struct irq_domain *domain;
-@@ -662,36 +575,8 @@ void __init gic_init_bases(unsigned int
- 
-       gic = &gic_data[gic_nr];
-       domain = &gic->domain;
--#ifdef CONFIG_GIC_NON_BANKED
--      if (percpu_offset) { /* Frankein-GIC without banked registers... */
--              unsigned int cpu;
--
--              gic->dist_base.percpu_base = alloc_percpu(void __iomem *);
--              gic->cpu_base.percpu_base = alloc_percpu(void __iomem *);
--              if (WARN_ON(!gic->dist_base.percpu_base ||
--                          !gic->cpu_base.percpu_base)) {
--                      free_percpu(gic->dist_base.percpu_base);
--                      free_percpu(gic->cpu_base.percpu_base);
--                      return;
--              }
--
--              for_each_possible_cpu(cpu) {
--                      unsigned long offset = percpu_offset * 
cpu_logical_map(cpu);
--                      *per_cpu_ptr(gic->dist_base.percpu_base, cpu) = 
dist_base + offset;
--                      *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) = cpu_base 
+ offset;
--              }
--
--              gic_set_base_accessor(gic, gic_get_percpu_base);
--      } else
--#endif
--      {                       /* Normal, sane GIC... */
--              WARN(percpu_offset,
--                   "GIC_NON_BANKED not enabled, ignoring %08x offset!",
--                   percpu_offset);
--              gic->dist_base.common_base = dist_base;
--              gic->cpu_base.common_base = cpu_base;
--              gic_set_base_accessor(gic, gic_get_common_base);
--      }
-+      gic->dist_base = dist_base;
-+      gic->cpu_base = cpu_base;
- 
-       /*
-        * For primary GICs, skip over SGIs.
-@@ -699,6 +584,8 @@ void __init gic_init_bases(unsigned int
-        */
-       domain->hwirq_base = 32;
-       if (gic_nr == 0) {
-+              gic_cpu_base_addr = cpu_base;
-+
-               if ((irq_start & 31) > 0) {
-                       domain->hwirq_base = 16;
-                       if (irq_start != -1)
-@@ -710,7 +597,7 @@ void __init gic_init_bases(unsigned int
-        * Find out how many interrupts are supported.
-        * The GIC only supports up to 1020 interrupt sources.
-        */
--      gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f;
-+      gic_irqs = readl_relaxed(dist_base + GIC_DIST_CTR) & 0x1f;
-       gic_irqs = (gic_irqs + 1) * 32;
-       if (gic_irqs > 1020)
-               gic_irqs = 1020;
-@@ -758,7 +645,7 @@ void gic_raise_softirq(const struct cpum
-       dsb();
- 
-       /* this always happens on GIC0 */
--      writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + 
GIC_DIST_SOFTINT);
-+      writel_relaxed(map << 16 | irq, gic_data[0].dist_base + 
GIC_DIST_SOFTINT);
- }
- #endif
- 
-@@ -769,7 +656,6 @@ int __init gic_of_init(struct device_nod
- {
-       void __iomem *cpu_base;
-       void __iomem *dist_base;
--      u32 percpu_offset;
-       int irq;
-       struct irq_domain *domain = &gic_data[gic_cnt].domain;
- 
-@@ -782,12 +668,9 @@ int __init gic_of_init(struct device_nod
-       cpu_base = of_iomap(node, 1);
-       WARN(!cpu_base, "unable to map gic cpu registers\n");
- 
--      if (of_property_read_u32(node, "cpu-offset", &percpu_offset))
--              percpu_offset = 0;
--
-       domain->of_node = of_node_get(node);
- 
--      gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset);
-+      gic_init(gic_cnt, -1, dist_base, cpu_base);
- 
-       if (parent) {
-               irq = irq_of_parse_and_map(node, 0);
---- a/arch/arm/mach-omap2/irq.c
-+++ b/arch/arm/mach-omap2/irq.c
-@@ -15,7 +15,6 @@
- #include <linux/interrupt.h>
- #include <linux/io.h>
- #include <mach/hardware.h>
--#include <asm/exception.h>
- #include <asm/mach/irq.h>
- 
- 
-@@ -36,11 +35,6 @@
- /* Number of IRQ state bits in each MIR register */
- #define IRQ_BITS_PER_REG      32
- 
--#define OMAP2_IRQ_BASE                OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE)
--#define OMAP3_IRQ_BASE                OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE)
--#define INTCPS_SIR_IRQ_OFFSET 0x0040  /* omap2/3 active interrupt offset */
--#define ACTIVEIRQ_MASK                0x7f    /* omap2/3 active interrupt 
bits */
--
- /*
-  * OMAP2 has a number of different interrupt controllers, each interrupt
-  * controller is identified as its own "bank". Register definitions are
-@@ -50,12 +44,10 @@
- static struct omap_irq_bank {
-       void __iomem *base_reg;
-       unsigned int nr_irqs;
--      unsigned int nr_regs_req;
- } __attribute__ ((aligned(4))) irq_banks[] = {
-       {
-               /* MPU INTC */
-               .nr_irqs        = 96,
--              .nr_regs_req    = 3,
-       },
- };
- 
-@@ -65,8 +57,8 @@ struct omap3_intc_regs {
-       u32 protection;
-       u32 idle;
-       u32 threshold;
--      u32 ilr[INTCPS_MAX_NR_IRQS];
--      u32 mir[INTCPS_MAX_NR_REGS_REQ];
-+      u32 ilr[INTCPS_NR_IRQS];
-+      u32 mir[INTCPS_NR_MIR_REGS];
- };
- 
- /* INTC bank register get/set */
-@@ -151,7 +143,6 @@ omap_alloc_gc(void __iomem *base, unsign
- 
- static void __init omap_init_irq(u32 base, int nr_irqs)
- {
--      void __iomem *omap_irq_base;
-       unsigned long nr_of_irqs = 0;
-       unsigned int nr_banks = 0;
-       int i, j;
-@@ -164,7 +155,6 @@ static void __init omap_init_irq(u32 bas
-               struct omap_irq_bank *bank = irq_banks + i;
- 
-               bank->nr_irqs = nr_irqs;
--              bank->nr_regs_req = 0;
- 
-               /* Static mapping, never released */
-               bank->base_reg = ioremap(base, SZ_4K);
-@@ -175,10 +165,8 @@ static void __init omap_init_irq(u32 bas
- 
-               omap_irq_bank_init_one(bank);
- 
--              for (j = 0; j < bank->nr_irqs; j += 32) {
-+              for (j = 0; j < bank->nr_irqs; j += 32)
-                       omap_alloc_gc(bank->base_reg + j, j, 32);
--                      bank->nr_regs_req++;
--              }
- 
-               nr_of_irqs += bank->nr_irqs;
-               nr_banks++;
-@@ -198,43 +186,11 @@ void __init omap3_init_irq(void)
-       omap_init_irq(OMAP34XX_IC_BASE, 96);
- }
- 
--void __init ti81xx_init_irq(void)
-+void __init ti816x_init_irq(void)
- {
-       omap_init_irq(OMAP34XX_IC_BASE, 128);
- }
- 
--static inline void omap_intc_handle_irq(void __iomem *base_addr,
--              unsigned int no_regs_req, struct pt_regs *regs)
--{
--      u32 irqnr = 0;
--
--      do {
--              int i = 0;
--
--              for (i = 0; i < no_regs_req; i++) {
--                      irqnr = readl_relaxed(base_addr + 0x98 + (0x20 * i));
--                      if (irqnr)
--                              goto out;
--              }
--
--out:
--              if (!irqnr)
--                      break;
--
--              irqnr = readl_relaxed(base_addr + INTCPS_SIR_IRQ_OFFSET);
--              irqnr &= ACTIVEIRQ_MASK;
--
--              if (irqnr)
--                      handle_IRQ(irqnr, regs);
--      } while (irqnr);
--}
--
--asmlinkage void __exception_irq_entry omap2_intc_handle_irq(struct pt_regs 
*regs)
--{
--      void __iomem *base_addr = OMAP2_IRQ_BASE;
--      omap_intc_handle_irq(base_addr, irq_banks[0].nr_regs_req, regs);
--}
--
- #ifdef CONFIG_ARCH_OMAP3
- static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];
- 
-@@ -251,10 +207,10 @@ void omap_intc_save_context(void)
-                       intc_bank_read_reg(bank, INTC_IDLE);
-               intc_context[ind].threshold =
-                       intc_bank_read_reg(bank, INTC_THRESHOLD);
--              for (i = 0; i < bank->nr_irqs; i++)
-+              for (i = 0; i < INTCPS_NR_IRQS; i++)
-                       intc_context[ind].ilr[i] =
-                               intc_bank_read_reg(bank, (0x100 + 0x4*i));
--              for (i = 0; i < bank->nr_regs_req; i++)
-+              for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
-                       intc_context[ind].mir[i] =
-                               intc_bank_read_reg(&irq_banks[0], INTC_MIR0 +
-                               (0x20 * i));
-@@ -277,10 +233,10 @@ void omap_intc_restore_context(void)
-                                       bank, INTC_IDLE);
-               intc_bank_write_reg(intc_context[ind].threshold,
-                                       bank, INTC_THRESHOLD);
--              for (i = 0; i < bank->nr_irqs; i++)
-+              for (i = 0; i < INTCPS_NR_IRQS; i++)
-                       intc_bank_write_reg(intc_context[ind].ilr[i],
-                               bank, (0x100 + 0x4*i));
--              for (i = 0; i < bank->nr_regs_req; i++)
-+              for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
-                       intc_bank_write_reg(intc_context[ind].mir[i],
-                                &irq_banks[0], INTC_MIR0 + (0x20 * i));
-       }
-@@ -307,10 +263,4 @@ void omap3_intc_resume_idle(void)
-       /* Re-enable autoidle */
-       intc_bank_write_reg(1, &irq_banks[0], INTC_SYSCONFIG);
- }
--
--asmlinkage void __exception_irq_entry omap3_intc_handle_irq(struct pt_regs 
*regs)
--{
--      void __iomem *base_addr = OMAP3_IRQ_BASE;
--      omap_intc_handle_irq(base_addr, irq_banks[0].nr_regs_req, regs);
--}
- #endif /* CONFIG_ARCH_OMAP3 */
---- a/arch/arm/plat-mxc/gic.c
-+++ b/arch/arm/plat-mxc/gic.c
-@@ -0,0 +1,41 @@
-+/*
-+ * Copyright 2011 Freescale Semiconductor, Inc.
-+ * Copyright 2011 Linaro Ltd.
-+ *
-+ * The code contained herein is licensed under the GNU General Public
-+ * License. You may obtain a copy of the GNU General Public License
-+ * Version 2 or later at the following locations:
-+ *
-+ * http://www.opensource.org/licenses/gpl-license.html
-+ * http://www.gnu.org/copyleft/gpl.html
-+ */
-+
-+#include <linux/io.h>
-+#include <asm/exception.h>
-+#include <asm/localtimer.h>
-+#include <asm/hardware/gic.h>
-+#ifdef CONFIG_SMP
-+#include <asm/smp.h>
-+#endif
-+
-+asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
-+{
-+      u32 irqstat, irqnr;
-+
-+      do {
-+              irqstat = readl_relaxed(gic_cpu_base_addr + GIC_CPU_INTACK);
-+              irqnr = irqstat & 0x3ff;
-+              if (irqnr == 1023)
-+                      break;
-+
-+              if (irqnr > 15 && irqnr < 1021)
-+                      handle_IRQ(irqnr, regs);
-+#ifdef CONFIG_SMP
-+              else {
-+                      writel_relaxed(irqstat, gic_cpu_base_addr +
-+                                              GIC_CPU_EOI);
-+                      handle_IPI(irqnr, regs);
-+              }
-+#endif
-+      } while (1);
-+}
---- a/arch/arm/plat-omap/include/plat/irqs.h
-+++ b/arch/arm/plat-omap/include/plat/irqs.h
-@@ -30,7 +30,6 @@
- 
- /* All OMAP4 specific defines are moved to irqs-44xx.h */
- #include "irqs-44xx.h"
--#include "irqs-33xx.h"
- 
- /*
-  * IRQ numbers for interrupt handler 1
-@@ -358,7 +357,7 @@
- #define INT_35XX_EMAC_C0_TX_PULSE_IRQ 69
- #define INT_35XX_EMAC_C0_MISC_PULSE_IRQ       70
- #define INT_35XX_USBOTG_IRQ           71
--#define INT_35XX_UART4_IRQ            84
-+#define INT_35XX_UART4                        84
- #define INT_35XX_CCDC_VD0_IRQ         88
- #define INT_35XX_CCDC_VD1_IRQ         92
- #define INT_35XX_CCDC_VD2_IRQ         93
-@@ -434,11 +433,22 @@
- 
- #define OMAP_IRQ_BIT(irq)     (1 << ((irq) % 32))
- 
--/*
-- * Max from AM33XX device
-- */
--#define INTCPS_MAX_NR_REGS_REQ        4
--#define INTCPS_MAX_NR_IRQS    128
-+#define INTCPS_NR_MIR_REGS    3
-+#define INTCPS_NR_IRQS                96
-+
-+#ifndef __ASSEMBLY__
-+extern void __iomem *omap_irq_base;
-+void omap1_init_irq(void);
-+void omap2_init_irq(void);
-+void omap3_init_irq(void);
-+void ti816x_init_irq(void);
-+extern int omap_irq_pending(void);
-+void omap_intc_save_context(void);
-+void omap_intc_restore_context(void);
-+void omap3_intc_suspend(void);
-+void omap3_intc_prepare_idle(void);
-+void omap3_intc_resume_idle(void);
-+#endif
- 
- #include <mach/hardware.h>
- 
diff --git 
a/ksrc/arch/arm/patches/beaglebone/ipipe-core-3.8.13-beaglebone-post.patch 
b/ksrc/arch/arm/patches/beaglebone/ipipe-core-3.8.13-beaglebone-post.patch
new file mode 100644
index 0000000..292b1c3
--- /dev/null
+++ b/ksrc/arch/arm/patches/beaglebone/ipipe-core-3.8.13-beaglebone-post.patch
@@ -0,0 +1,16 @@
+diff -uPr ipipe/arch/arm/mach-omap2/gpmc.c post/arch/arm/mach-omap2/gpmc.c
+--- ipipe/arch/arm/mach-omap2/gpmc.c   2013-08-27 20:34:22.366199351 +0200
++++ post/arch/arm/mach-omap2/gpmc.c    2013-08-27 20:16:56.990703412 +0200
+@@ -25,6 +25,12 @@
+ #include <linux/module.h>
+ #include <linux/interrupt.h>
+ #include <linux/platform_device.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <linux/of_mtd.h>
++#include <linux/of_device.h>
++#include <linux/mtd/nand.h>
++#include <linux/pinctrl/consumer.h>
+ #include <linux/ipipe.h>
+ 
+ #include <linux/platform_data/mtd-nand-omap2.h>
diff --git 
a/ksrc/arch/arm/patches/beaglebone/ipipe-core-3.8.13-beaglebone-pre.patch 
b/ksrc/arch/arm/patches/beaglebone/ipipe-core-3.8.13-beaglebone-pre.patch
new file mode 100644
index 0000000..aa37724
--- /dev/null
+++ b/ksrc/arch/arm/patches/beaglebone/ipipe-core-3.8.13-beaglebone-pre.patch
@@ -0,0 +1,16 @@
+diff -uPr bb/arch/arm/mach-omap2/gpmc.c pre/arch/arm/mach-omap2/gpmc.c
+--- bb/arch/arm/mach-omap2/gpmc.c      2013-08-27 20:26:55.080672567 +0200
++++ pre/arch/arm/mach-omap2/gpmc.c     2013-08-27 20:31:15.727578153 +0200
+@@ -25,12 +25,6 @@
+ #include <linux/module.h>
+ #include <linux/interrupt.h>
+ #include <linux/platform_device.h>
+-#include <linux/of.h>
+-#include <linux/of_address.h>
+-#include <linux/of_mtd.h>
+-#include <linux/of_device.h>
+-#include <linux/mtd/nand.h>
+-#include <linux/pinctrl/consumer.h>
+ 
+ #include <linux/platform_data/mtd-nand-omap2.h>
+ 


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