Author: Philippe Gerum <r...@xenomai.org>
Date: Thu Sep 17 11:43:50 2015 +0200
cobalt/arm64: restrict unlocked switch to SMP
Unlocked switching for Xenomai/ARM was specifically introduced for
improving the interrupt latency on low-end armv4/armv5 platforms with
The once massive overhead imposed on the MMU context switching code
for invalidating the cache is long gone with VIPT indexing, and
keeping IRQs off while switching the memory context on armv8 these
days is not an issue. Actually, the complexity of the code involved in
dealing with unlocked switching may overbalance the expected gain.
However, the mainline kernel implementation for ASID management in the
SMP case currently requires us to keep IRQs enabled when allocating a
new MM context over the Xenomai domain, just like it did for aarch32
during the 2.6.3x time frame until the IPI-based approach was
So, let's restrict unlocked switching to the SMP case, forcing it off
otherwise, in the hope we can drop it entirely in the future.
At this chance, CONFIG_IPIPE_WANT_PREEMPTIBLE_SWITCH moves to the
kernel area, where it actually belongs.
kernel/cobalt/arch/arm64/Kconfig | 21 +--------------------
1 file changed, 1 insertion(+), 20 deletions(-)
diff --git a/kernel/cobalt/arch/arm64/Kconfig b/kernel/cobalt/arch/arm64/Kconfig
index dc6485d..927c647 100644
@@ -1,27 +1,8 @@
-menu "Machine/platform-specific options"
- bool "Unlocked context switch"
- default y
- The Cobalt core may allow non-atomic execution of the
- machine-dependent context switching code, so that other CPUs
- and/or local interrupts may execute concurrently.
- This option reduces interrupt latency when costly cache and
- TLB flushes are required to switch context.
- You definitely want to enable that option on low-end ARM
- default y if XENO_ARCH_UNLOCKED_SWITCH
- default n if !XENO_ARCH_UNLOCKED_SWITCH
+ def_bool IPIPE_WANT_PREEMPTIBLE_SWITCH
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